ICE40 version

sinara-hw · Sep 8, 2019 · 809b7ca · 809b7ca
1 parent fec8ff8
commit 809b7ca
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Showing 13 changed files with 20 additions and 13 deletions.
diff --git a/PCB/Fastino.OutJob b/PCB/Fastino.OutJob
@@ -15,7 +15,7 @@ LifeCycleDefinitionGUID=
 RevisionNamingSchemeGUID=
 
 [OutputGroup1]
-Name=Zotino.OutJob
+Name=Fastino.OutJob
 Description=
 TargetOutputMedium=PDF
 VariantName=QFN
@@ -273,17 +273,19 @@ OutputEnabled11_OutputMedium4=0
 OutputEnabled11_OutputMedium5=0
 OutputDefault11=0
 PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+Configuration11_Name1=OutputConfigurationParameter1
+Configuration11_Item1=Record=LayerStackReportView|Units=Imperial
 
 [PublishSettings]
-OutputFilePath2=D:\Dropbox\DESIGNS\MTCA_projects\SINARA\ARTIQ_ALTIUM\EEMs\Zotino\PCB\Project Outputs for Zotino\Zotino.PDF
+OutputFilePath2=D:\Dropbox\DESIGNS\Sinara_ALTIUM\EEMs\Fastino\PCB\Project Outputs for Fastino\Zotino.PDF
 ReleaseManaged2=0
-OutputBasePath2=Project Outputs for Zotino\
+OutputBasePath2=Project Outputs for Fastino\
 OutputPathMedia2=
 OutputPathMediaValue2=
 OutputPathOutputer2=[Output Type]
 OutputPathOutputerPrefix2=
 OutputPathOutputerValue2=
-OutputFileName2=Zotino
+OutputFileName2=Fastino
 OutputFileNameMulti2=
 UseOutputNameForMulti2=0
 OutputFileNameSpecial2=
@@ -302,9 +304,9 @@ ShowComponentParameters2=1
 GlobalBookmarks2=0
 PDFACompliance2=Disabled
 PDFVersion2=Default
-OutputFilePath3=D:\Dropbox\DESIGNS\Sinara_ALTIUM\EEMs\Zotino\PCB\Project Outputs for Zotino\
+OutputFilePath3=D:\Dropbox\DESIGNS\Sinara_ALTIUM\EEMs\Fastino\PCB\Project Outputs for Fastino\
 ReleaseManaged3=0
-OutputBasePath3=Project Outputs for Zotino\
+OutputBasePath3=Project Outputs for Fastino\
 OutputPathMedia3=
 OutputPathMediaValue3=
 OutputPathOutputer3=[Output Type]
@@ -352,15 +354,15 @@ FFmpegPixelFormat4=0
 FFmpegQuality4=80
 WmvVideoCodecName4=Windows Media Video V7
 WmvQuality4=80
-OutputFilePath5=D:\Dropbox\DESIGNS\Sinara_ALTIUM\EEMs\Zotino\PCB\Project Outputs for Zotino\Zotino.PDF
-ReleaseManaged5=1
-OutputBasePath5=Project Outputs for Fastino
+OutputFilePath5=D:\Dropbox\DESIGNS\Sinara_ALTIUM\EEMs\Fastino\PCB\Project Outputs for Fastino\Zotino-shematics.PDF
+ReleaseManaged5=0
+OutputBasePath5=Project Outputs for Fastino\
 OutputPathMedia5=
 OutputPathMediaValue5=
 OutputPathOutputer5=[Output Type]
 OutputPathOutputerPrefix5=
 OutputPathOutputerValue5=
-OutputFileName5=Zotino-shematics.PDF
+OutputFileName5=Fastino-shematics.PDF
 OutputFileNameMulti5=
 UseOutputNameForMulti5=0
 OutputFileNameSpecial5=
@@ -381,9 +383,9 @@ PDFACompliance5=Disabled
 PDFVersion5=Default
 
 [GeneratedFilesSettings]
-RelativeOutputPath2=D:\Dropbox\DESIGNS\MTCA_projects\SINARA\ARTIQ_ALTIUM\EEMs\Zotino\PCB\Project Outputs for Zotino\Zotino.PDF
+RelativeOutputPath2=D:\Dropbox\DESIGNS\Sinara_ALTIUM\EEMs\Fastino\PCB\Project Outputs for Fastino\Zotino.PDF
 OpenOutputs2=1
-RelativeOutputPath3=D:\Dropbox\DESIGNS\Sinara_ALTIUM\EEMs\Zotino\PCB\Project Outputs for Zotino\
+RelativeOutputPath3=D:\Dropbox\DESIGNS\Sinara_ALTIUM\EEMs\Fastino\PCB\Project Outputs for Fastino\
 OpenOutputs3=0
 AddToProject3=0
 TimestampFolder3=0
@@ -395,6 +397,6 @@ OpenIPCOutput3=0
 EnableReload3=0
 RelativeOutputPath4=
 OpenOutputs4=1
-RelativeOutputPath5=D:\Dropbox\DESIGNS\Sinara_ALTIUM\EEMs\Zotino\PCB\Project Outputs for Zotino\Zotino.PDF
+RelativeOutputPath5=D:\Dropbox\DESIGNS\Sinara_ALTIUM\EEMs\Fastino\PCB\Project Outputs for Fastino\Zotino-shematics.PDF
 OpenOutputs5=1
 
diff --git a/PCB/Fastino.PCBDOC b/PCB/Fastino.PCBDOC
diff --git a/PCB/Fastino.schdoc b/PCB/Fastino.schdoc
diff --git a/PCB/Fastino_DAC_channel.SchDoc b/PCB/Fastino_DAC_channel.SchDoc
diff --git a/PCB/Fastino_FPGA.Harness b/PCB/Fastino_FPGA.Harness
@@ -0,0 +1,2 @@
+FPGA_CFG=CFG_RELOAD,FPGA_CSBSEL0,FPGA_CSBSEL1,FPGA_SDO,FPGA_SDI,FPGA_SCK,FPGA_SS,FPGA_CDONE,FPGA_CRESET
+I2C=SCL,SDA
diff --git a/PCB/Fastino_FPGA.SchDoc b/PCB/Fastino_FPGA.SchDoc
diff --git a/PCB/Fastino_FPGA_Config.Harness b/PCB/Fastino_FPGA_Config.Harness
@@ -0,0 +1,2 @@
+FPGA_CFG=CFG_RELOAD,FPGA_CSBSEL0,FPGA_CSBSEL1,FPGA_SDO,FPGA_SDI,FPGA_SCK,FPGA_SS,FPGA_CDONE,FPGA_CRESET
+I2C=SCL,SDA
diff --git a/PCB/Fastino_FPGA_Config.SchDoc b/PCB/Fastino_FPGA_Config.SchDoc
diff --git a/PCB/Fastino_FPGA_LVDS.Harness b/PCB/Fastino_FPGA_LVDS.Harness
@@ -0,0 +1 @@
+I2C=SDA,SCL
diff --git a/PCB/Fastino_FPGA_LVDS.SchDoc b/PCB/Fastino_FPGA_LVDS.SchDoc
diff --git a/PCB/Fastino_FPGA_Supply.SchDoc b/PCB/Fastino_FPGA_Supply.SchDoc
diff --git a/PCB/Fastino_References.SchDoc b/PCB/Fastino_References.SchDoc
diff --git a/PCB/Fastino_Supply.SchDoc b/PCB/Fastino_Supply.SchDoc