Merge branch 'master' of https://github.com/sinara-hw/Fastino

SIM_CALC/Output stage/Design.asc

@@ -0,0 +1,143 @@
+Version 4
+SHEET 1 1260 680
+WIRE 128 128 128 112
+WIRE 240 128 240 112
+WIRE 352 128 352 112
+WIRE 560 128 560 96
+WIRE 128 144 128 128
+WIRE 240 144 240 128
+WIRE 352 144 352 128
+WIRE 560 144 560 128
+WIRE 608 144 592 144
+WIRE 704 144 672 144
+WIRE 944 224 848 224
+WIRE 1104 224 1008 224
+WIRE 128 240 128 224
+WIRE 240 240 240 224
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+WIRE 560 240 560 224
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+WIRE 592 240 560 240
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+WIRE 464 368 320 368
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+WIRE 592 368 560 368
+WIRE 976 368 976 352
+WIRE 560 384 560 368
+WIRE 144 400 144 368
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+WIRE 144 496 144 480
+FLAG 240 240 0
+FLAG 240 128 V+
+FLAG 352 240 0
+FLAG 352 128 V-
+FLAG 624 320 V+
+FLAG 624 384 V-
+FLAG 144 496 0
+FLAG 128 240 0
+FLAG 128 128 Vref
+FLAG 560 128 Vref
+FLAG 448 272 0
+FLAG 560 448 0
+FLAG 1040 304 V+
+FLAG 1040 368 V-
+FLAG 976 448 0
+FLAG 1184 336 OUT
+SYMBOL Opamps/opamp2 624 288 R0
+SYMATTR InstName U1
+SYMATTR Value OPA197
+SYMBOL voltage 240 128 R0
+SYMATTR InstName V1
+SYMATTR Value 13
+SYMBOL voltage 352 128 R0
+SYMATTR InstName V2
+SYMATTR Value -13
+SYMBOL voltage 144 384 R0
+WINDOW 123 24 118 Left 2
+SYMATTR Value2 AC 1
+SYMATTR InstName V3
+SYMATTR Value PULSE(0 {Vref} 10u 10n 10n 10u)
+SYMBOL res 336 352 R90
+WINDOW 0 0 56 VBottom 2
+WINDOW 3 32 56 VTop 2
+SYMATTR InstName R1
+SYMATTR Value {Rdac}
+SYMBOL res 576 128 M0
+SYMATTR InstName R4
+SYMATTR Value {Rinv/2}
+SYMBOL res 704 224 R90
+WINDOW 0 0 56 VBottom 2
+WINDOW 3 32 56 VTop 2
+SYMATTR InstName R5
+SYMATTR Value {Rinv}
+SYMBOL voltage 128 128 R0
+SYMATTR InstName V4
+SYMATTR Value {Vref}
+SYMBOL res 560 256 R90
+WINDOW 0 0 56 VBottom 2
+WINDOW 3 32 56 VTop 2
+SYMATTR InstName R3
+SYMATTR Value {Rinv}
+SYMBOL cap 544 384 R0
+WINDOW 0 26 15 Left 2
+WINDOW 3 27 47 Left 2
+SYMATTR InstName C2
+SYMATTR Value 47p
+SYMBOL res 560 352 R90
+WINDOW 0 0 56 VBottom 2
+WINDOW 3 32 56 VTop 2
+SYMATTR InstName R6
+SYMATTR Value 0
+SYMBOL cap 672 128 R90
+WINDOW 0 0 32 VBottom 2
+WINDOW 3 32 32 VTop 2
+SYMATTR InstName C1
+SYMATTR Value 10p
+SYMBOL res 832 336 R90
+WINDOW 0 0 56 VBottom 2
+WINDOW 3 32 56 VTop 2
+SYMATTR InstName R2
+SYMATTR Value 1.47k
+SYMBOL res 960 336 R90
+WINDOW 0 0 56 VBottom 2
+WINDOW 3 32 56 VTop 2
+SYMATTR InstName R7
+SYMATTR Value 1.69k
+SYMBOL cap 1008 208 R90
+WINDOW 0 0 32 VBottom 2
+WINDOW 3 32 32 VTop 2
+SYMATTR InstName C3
+SYMATTR Value 360p
+SYMBOL Opamps/opamp2 1040 272 R0
+SYMATTR InstName U2
+SYMATTR Value OPA197
+SYMBOL cap 992 432 R180
+WINDOW 0 24 56 Left 2
+WINDOW 3 24 8 Left 2
+SYMATTR InstName C4
+SYMATTR Value 100p
+TEXT 64 568 Left 2 !.include OPA197.lib\n.param Rdac 6.2k\n.param Rinv 10k\n.param Vref 5.5
+TEXT 312 584 Left 2 !;.tran 30u\n;.ac dec 100 1k 100Meg\n.noise V(OUT) V3 dec 100 100 100Meg

SIM_CALC/Output stage/README.txt

@@ -0,0 +1,27 @@
+LTspice output stage simulations
+================================
+
+This directory contains the LTspice source files used in the 
+design phase of the Fastino output stage.
+
+ - Design.asc: The proposed output stage design.
+ - Design Monte-Carlo tolerance analysis.asc: A component
+   tolerance analysis for the proposed design (mc() in LTspice
+   uniformly samples from the given relative tolerance region).
+ - Design with MFB second stage.asc: An alternative design
+   providing enhanced high-frequency roll-off at the cost of an
+   extra matched resistor pair and slightly increased noise and
+   power dissipation.
+ - Noise estimate using DAC matched Rs.asc: A quick estimate of
+   the output noise from the DAC-internal matched resistor pair.
+ - Stabilizer output stage design.asc: For comparison, the
+   output stage of the Stabilizer v1.0 two-channel
+   microcontroller servo.
+
+The macromodels for the OPA197 and AD8620 can be downloaded from
+the respective manufacturer's websites; place them somewhere on
+the library search path (in the easiest case, this directory):
+
+ - http://www.ti.com/product/OPA197/toolssoftware
+   (the PSpice model can be used with LTSpice)
+ - https://www.analog.com/media/en/simulation-models/spice-models/ad8620.cir

SIM_CALC/Output stage/Stabilizer output stage design.asc

@@ -0,0 +1,157 @@
+Version 4
+SHEET 1 1260 680
+WIRE 128 128 128 112
+WIRE 240 128 240 112
+WIRE 352 128 352 112
+WIRE 560 128 560 96
+WIRE 1040 128 1008 128
+WIRE 1120 128 1104 128
+WIRE 128 144 128 128
+WIRE 240 144 240 128
+WIRE 352 144 352 128
+WIRE 560 144 560 128
+WIRE 624 160 592 160
+WIRE 704 160 688 160
+WIRE 912 224 880 224
+WIRE 1008 224 1008 128
+WIRE 1008 224 992 224
+WIRE 1024 224 1008 224
+WIRE 1120 224 1120 128
+WIRE 1120 224 1104 224
+WIRE 128 240 128 224
+WIRE 240 240 240 224
+WIRE 352 240 352 224
+WIRE 560 240 560 224
+WIRE 592 240 592 160
+WIRE 592 240 560 240
+WIRE 608 240 592 240
+WIRE 704 240 704 160
+WIRE 704 240 688 240
+WIRE 1008 320 1008 224
+WIRE 1024 320 1008 320
+WIRE 560 336 560 240
+WIRE 592 336 560 336
+WIRE 1120 336 1120 224
+WIRE 1120 336 1088 336
+WIRE 1200 336 1120 336
+WIRE 704 352 704 240
+WIRE 704 352 656 352
+WIRE 736 352 704 352
+WIRE 848 352 816 352
+WIRE 880 352 848 352
+WIRE 992 352 960 352
+WIRE 1024 352 992 352
+WIRE 240 368 144 368
+WIRE 464 368 320 368
+WIRE 560 368 544 368
+WIRE 592 368 560 368
+WIRE 992 368 992 352
+WIRE 560 384 560 368
+WIRE 144 400 144 368
+WIRE 992 448 992 432
+WIRE 144 496 144 480
+WIRE 848 512 848 352
+WIRE 992 512 848 512
+WIRE 1120 512 1120 336
+WIRE 1120 512 1056 512
+FLAG 240 240 0
+FLAG 240 128 V+
+FLAG 352 240 0
+FLAG 352 128 V-
+FLAG 624 320 V+
+FLAG 624 384 V-
+FLAG 144 496 0
+FLAG 128 240 0
+FLAG 128 128 Vref
+FLAG 560 128 Vref
+FLAG 560 448 0
+FLAG 1056 304 V+
+FLAG 1056 368 V-
+FLAG 992 448 0
+FLAG 1200 336 OUT
+FLAG 880 224 0
+SYMBOL Opamps/opamp2 624 288 R0
+SYMATTR InstName U1
+SYMATTR Value AD8620
+SYMBOL voltage 240 128 R0
+SYMATTR InstName V1
+SYMATTR Value 13
+SYMBOL voltage 352 128 R0
+SYMATTR InstName V2
+SYMATTR Value -13
+SYMBOL voltage 144 384 R0
+WINDOW 123 24 118 Left 2
+SYMATTR Value2 AC 1
+SYMATTR InstName V3
+SYMATTR Value PULSE(0 {0.49 * Vref} 0 10n 10n 10u)
+SYMBOL res 336 352 R90
+WINDOW 0 0 56 VBottom 2
+WINDOW 3 32 56 VTop 2
+SYMATTR InstName R1
+SYMATTR Value {Rdac}
+SYMBOL res 576 128 M0
+SYMATTR InstName R4
+SYMATTR Value {Rinv}
+SYMBOL res 704 224 R90
+WINDOW 0 0 56 VBottom 2
+WINDOW 3 32 56 VTop 2
+SYMATTR InstName R5
+SYMATTR Value {Rinv}
+SYMBOL voltage 128 128 R0
+SYMATTR InstName V4
+SYMATTR Value {Vref}
+SYMBOL cap 544 384 R0
+WINDOW 0 26 15 Left 2
+WINDOW 3 27 47 Left 2
+SYMATTR InstName C2
+SYMATTR Value 3.3p
+SYMBOL res 560 352 R90
+WINDOW 0 0 56 VBottom 2
+WINDOW 3 32 56 VTop 2
+SYMATTR InstName R6
+SYMATTR Value 10k
+SYMBOL res 832 336 R90
+WINDOW 0 0 56 VBottom 2
+WINDOW 3 32 56 VTop 2
+SYMATTR InstName R2
+SYMATTR Value 560
+SYMBOL res 976 336 R90
+WINDOW 0 0 56 VBottom 2
+WINDOW 3 32 56 VTop 2
+SYMATTR InstName R7
+SYMATTR Value 1.58k
+SYMBOL cap 1056 496 R90
+WINDOW 0 0 32 VBottom 2
+WINDOW 3 32 32 VTop 2
+SYMATTR InstName C3
+SYMATTR Value 220p
+SYMBOL Opamps/opamp2 1056 272 R0
+SYMATTR InstName U2
+SYMATTR Value AD8620
+SYMBOL cap 1008 432 R180
+WINDOW 0 24 56 Left 2
+WINDOW 3 24 8 Left 2
+SYMATTR InstName C4
+SYMATTR Value 220p
+SYMBOL res 1008 208 R90
+WINDOW 0 0 56 VBottom 2
+WINDOW 3 32 56 VTop 2
+SYMATTR InstName R3
+SYMATTR Value 10k
+SYMBOL res 1120 208 R90
+WINDOW 0 0 56 VBottom 2
+WINDOW 3 32 56 VTop 2
+SYMATTR InstName R8
+SYMATTR Value 15k
+SYMBOL cap 1104 112 R90
+WINDOW 0 0 32 VBottom 2
+WINDOW 3 32 32 VTop 2
+SYMATTR InstName C1
+SYMATTR Value 7.5p
+SYMBOL cap 688 144 R90
+WINDOW 0 0 32 VBottom 2
+WINDOW 3 32 32 VTop 2
+SYMATTR InstName C5
+SYMATTR Value 15p
+TEXT 64 568 Left 2 !.include AD8620.cir\n.param Rdac 6.2k\n.param Rinv 28k\n.param Vref 4.096
+TEXT 312 584 Left 2 !;.tran 10u\n.ac dec 100 1k 100Meg\n;.noise V(OUT) V3 dec 100 100 100Meg