adjust load/store timings according to official v810 manual

skyfloogle · Apr 7, 2024 · 3758118 · 3758118
1 parent 26e074f
commit 3758118
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Showing 2 changed files with 13 additions and 19 deletions.
diff --git a/source/common/drc_core.c b/source/common/drc_core.c
@@ -1159,12 +1159,12 @@ static int drc_translateBlock() {
                 }
 
                 if (i > 0 && (inst_cache[i - 1].opcode & 0x34) == 0x30 && (inst_cache[i - 1].opcode & 3) != 2) {
-                    // load immediately following another load takes 4 cycles instead of 5
+                    // load immediately following another load takes 2 cycles instead of 3
                     cycles -= 1;
                 } else if (i > 0 && opcycle[inst_cache[i - 1].opcode] > 4) {
                     // load following instruction taking "many" cycles only takes 1 cycles
                     // guessing "many" is 4 for now
-                    cycles -= 4;
+                    cycles -= 2;
                 }
                 break;
             case V810_OP_LD_H: // ld.h disp16 [reg1], reg2
@@ -1190,12 +1190,12 @@ static int drc_translateBlock() {
                 }
 
                 if (i > 0 && (inst_cache[i - 1].opcode & 0x34) == 0x30 && (inst_cache[i - 1].opcode & 3) != 2) {
-                    // load immediately following another load takes 4 cycles instead of 5
+                    // load immediately following another load takes 2 cycles instead of 3
                     cycles -= 1;
                 } else if (i > 0 && opcycle[inst_cache[i - 1].opcode] > 4) {
                     // load following instruction taking "many" cycles only takes 1 cycles
                     // guessing "many" is 4 for now
-                    cycles -= 4;
+                    cycles -= 2;
                 }
                 break;
             case V810_OP_LD_W: // ld.w disp16 [reg1], reg2
@@ -1238,11 +1238,9 @@ static int drc_translateBlock() {
                 ADD_I(2, 2, DRC_RELOC_WBYTE*4, 0);
                 BLX(ARM_COND_AL, 2);
 
-                if (i > 1 && (inst_cache[i - 1].opcode & 0x34) == 0x34 && (inst_cache[i - 1].opcode & 3) != 2
-                    && (inst_cache[i - 1].opcode & 0x34) == 0x34 && (inst_cache[i - 1].opcode & 3) != 2
-                ) {
-                    // with three consecutive stores, the third takes 4 cycles instead of 1
-                    cycles += 3;
+                if (i > 1 && (inst_cache[i - 1].opcode & 0x34) == 0x34 && (inst_cache[i - 1].opcode & 3) != 2) {
+                    // with two consecutive stores, the second takes 2 cycles instead of 1
+                    cycles += 1;
                 }
                 break;
             case V810_OP_ST_H:  // st.h reg2, disp16 [reg1]
@@ -1262,11 +1260,9 @@ static int drc_translateBlock() {
                 ADD_I(2, 2, DRC_RELOC_WHWORD*4, 0);
                 BLX(ARM_COND_AL, 2);
 
-                if (i > 1 && (inst_cache[i - 1].opcode & 0x34) == 0x34 && (inst_cache[i - 1].opcode & 3) != 2
-                    && (inst_cache[i - 1].opcode & 0x34) == 0x34 && (inst_cache[i - 1].opcode & 3) != 2
-                ) {
-                    // with three consecutive stores, the third takes 4 cycles instead of 1
-                    cycles += 3;
+                if (i > 1 && (inst_cache[i - 1].opcode & 0x34) == 0x34 && (inst_cache[i - 1].opcode & 3) != 2) {
+                    // with two consecutive stores, the second takes 2 cycles instead of 1
+                    cycles += 1;
                 }
                 break;
             case V810_OP_ST_W:  // st.h reg2, disp16 [reg1]
@@ -1286,10 +1282,8 @@ static int drc_translateBlock() {
                 ADD_I(2, 2, DRC_RELOC_WWORD*4, 0);
                 BLX(ARM_COND_AL, 2);
 
-                if (i > 1 && (inst_cache[i - 1].opcode & 0x34) == 0x34 && (inst_cache[i - 1].opcode & 3) != 2
-                    && (inst_cache[i - 1].opcode & 0x34) == 0x34 && (inst_cache[i - 1].opcode & 3) != 2
-                ) {
-                    // with three consecutive stores, the third takes 4 cycles instead of 1
+                if (i > 1 && (inst_cache[i - 1].opcode & 0x34) == 0x34 && (inst_cache[i - 1].opcode & 3) != 2) {
+                    // with two consecutive stores, the second takes 4 cycles instead of 1
                     cycles += 3;
                 }
 

diff --git a/source/common/v810_cpu.c b/source/common/v810_cpu.c
@@ -33,7 +33,7 @@ const BYTE opcycle[0x50] = {
     0x01,0x01,0x01,0x01,0x01,0x01,0x03,0x01,0x0D,0x26,0x0D,0x24,0x01,0x01,0x01,0x01,
     0x01,0x01,0x01,0x01,0x01,0x01,0x0C,0x01,0x0F,0x0A,0x05,0x00,0x08,0x08,0x0C,0x00, //EI, HALT, LDSR, STSR, DI, BSTR -- Unknown clocks
     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x03,0x03,0x01,0x01,0x01,0x01,
-    0x05,0x05,0x0D,0x05,0x01,0x01,0x00,0x01,0x05,0x05,0x1A,0x05,0x01,0x01,0x00,0x01, //these are based on 16-bit bus!! (should be 32-bit?)
+    0x03,0x03,0x0D,0x05,0x01,0x01,0x00,0x01,0x03,0x03,0x1A,0x05,0x01,0x01,0x00,0x01, //these are based on 16-bit bus!! (should be 32-bit?)
     0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x01,0x03,0x03
 };