further improve instruction timing accuracy

skyfloogle · Jan 8, 2024 · df05f7b · df05f7b
1 parent 3e0f09e
commit df05f7b
Show file tree

Hide file tree

Showing 3 changed files with 21 additions and 1 deletion.
diff --git a/include/arm_emit.h b/include/arm_emit.h
@@ -397,6 +397,11 @@ static inline void new_floating_point(BYTE cond, BYTE opc1, BYTE opc2, BYTE b12,
 #define ADDS_I(Rd, Rn, imm8, rot) \
     new_data_proc_imm(ARM_COND_AL, ARM_OP_ADD, 1, Rn, Rd, rot, imm8)
 
+// sub Rd, Rn, imm8, ror #rot
+// Subtract immediate
+#define SUB_I(Rd, Rn, imm8, rot) \
+    new_data_proc_imm(ARM_COND_AL, ARM_OP_SUB, 0, Rn, Rd, rot, imm8)
+
 // orr Rd, imm, ror #rot
 // Or immediate
 // imm8 can be rotated an even number of times

diff --git a/source/common/drc_core.c b/source/common/drc_core.c
@@ -833,6 +833,8 @@ int drc_translateBlock(exec_block *block) {
                     }
                     B(arm_cond, 0);
                 }
+                // branch not taken, so it only took 1 cycle
+                SUB_I(10, 10, 1, 0);
                 break;
             // Special case: bnh and bh can't be directly translated to ARM
             case V810_OP_BNH:
@@ -848,6 +850,8 @@ int drc_translateBlock(exec_block *block) {
                     B(ARM_COND_CS, 0);
                     B(ARM_COND_EQ, 0);
                 }
+                // branch not taken, so it only took 1 cycle
+                SUB_I(10, 10, 1, 0);
                 break;
             case V810_OP_BH:
                 if (inst_cache[i].busywait) {
@@ -863,6 +867,8 @@ int drc_translateBlock(exec_block *block) {
                     Boff(ARM_COND_EQ, 2);
                     B(ARM_COND_AL, 0);
                 }
+                // branch not taken, so it only took 1 cycle
+                SUB_I(10, 10, 1, 0);
                 break;
             case V810_OP_MOVHI: // movhi imm16, reg1, reg2:
                 MOV_I(0, (inst_cache[i].imm >> 8), 8);
@@ -1135,6 +1141,15 @@ int drc_translateBlock(exec_block *block) {
                     ADD(0, 0, arm_reg1);
                 }
 
+                if (i > 0 && (inst_cache[i - 1].opcode & 0x34) == 0x30 && (inst_cache[i - 1].opcode & 3) != 2) {
+                    // load immediately following another load takes 4 cycles instead of 5
+                    SUB_I(10, 10, 1, 0);
+                } else if (i > 0 && opcycle[inst_cache[i - 1].opcode] > 4) {
+                    // load following instruction taking "many" cycles only takes 1 cycles
+                    // guessing "many" is 4 for now
+                    SUB_I(10, 10, 4, 0);
+                }
+
                 LDR_IO(1, 11, 69 * 4);
                 ADD_I(1, 1, DRC_RELOC_RHWORD*4, 0);
                 BLX(ARM_COND_AL, 1);

diff --git a/source/common/v810_cpu.c b/source/common/v810_cpu.c
@@ -25,7 +25,7 @@ const BYTE opcycle[0x50] = {
     0x01,0x01,0x01,0x01,0x01,0x01,0x0C,0x01,0x0F,0x0A,0x05,0x00,0x08,0x08,0x0C,0x00, //EI, HALT, LDSR, STSR, DI, BSTR -- Unknown clocks
     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x03,0x03,0x01,0x01,0x01,0x01,
     0x05,0x05,0x0D,0x05,0x05,0x05,0x00,0x05,0x05,0x05,0x1A,0x05,0x05,0x05,0x00,0x05, //these are based on 16-bit bus!! (should be 32-bit?)
-    0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02
+    0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x01,0x03,0x03
 };
 
 int v810_init(char *rom_name) {