Upgrade to v5.14 and some fixes #2

The SBI SRST extension provides a standard way to poweroff and reboot the system irrespective to whether Linux RISC-V S-mode is running natively (HS-mode) or inside Guest/VM (VS-mode). The SBI SRST extension is available in latest SBI v0.3-draft specification at: https://github.com/riscv/riscv-sbi-doc. This patch extends Linux RISC-V SBI implementation to detect and use SBI SRST extension. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]>

We force select CPU_PM and provide asm/cpuidle.h so that we can use CPU IDLE drivers for Linux RISC-V kernel. Signed-off-by: Anup Patel <[email protected]>

The low-level relocate() function enables mmu and relocates execution to link-time addresses. We rename relocate() function to relocate_enable_mmu() function which is more informative. Also, the relocate_enable_mmu() function will be used in the resume path when a CPU wakes-up from a non-retentive suspend so we make it global symbol. Signed-off-by: Anup Patel <[email protected]>

The hart registers and CSRs are not preserved in non-retentative suspend state so we provide arch specific helper functions which will save/restore hart context upon entry/exit to non-retentive suspend state. These helper functions can be used by cpuidle drivers for non-retentive suspend entry/exit. Signed-off-by: Anup Patel <[email protected]>

We add defines related to SBI HSM suspend call and also update HSM states naming as-per latest SBI specification. Signed-off-by: Anup Patel <[email protected]>

The generic power domain related code in PSCI domain driver is largely independent of PSCI and can be shared with RISC-V SBI domain driver hence we factor-out this code into dt_idle_genpd.c and dt_idle_genpd.h. Signed-off-by: Anup Patel <[email protected]>

The RISC-V SBI HSM extension provides HSM suspend call which can be used by Linux RISC-V to enter platform specific low-power state. This patch adds a CPU idle driver based on RISC-V SBI calls which will populate idle states from device tree and use SBI calls to entry these idle states. Signed-off-by: Anup Patel <[email protected]>

Signed-off-by: Samuel Holland <[email protected]>

The RISC-V CPU idle states will be described in under the /cpus/idle-states DT node in the same way as ARM CPU idle states. This patch adds common bindings documentation for both ARM and RISC-V idle states. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Rob Herring <[email protected]>

We enable RISC-V SBI CPU Idle driver for QEMU virt machine to test SBI HSM Supend on QEMU. Signed-off-by: Anup Patel <[email protected]>

This config allows to compile 64b kernel as PIE and to relocate it at any virtual address at runtime: this paves the way to KASLR. Runtime relocation is possible since relocation metadata are embedded into the kernel. Note that relocating at runtime introduces an overhead even if the kernel is loaded at the same address it was linked at and that the compiler options are those used in arm64 which uses the same RELA relocation format. Signed-off-by: Alexandre Ghiti <[email protected]>

Relocating kernel at runtime is done very early in the boot process, so it is not convenient to check for relocations there and react in case a relocation was not expected. Powerpc architecture has a script that allows to check at compile time for such unexpected relocations: extract the common logic to scripts/ so that other architectures can take advantage of it. Signed-off-by: Alexandre Ghiti <[email protected]> Reviewed-by: Anup Patel <[email protected]> Acked-by: Michael Ellerman <[email protected]> (powerpc)

Relocating kernel at runtime is done very early in the boot process, so it is not convenient to check for relocations there and react in case a relocation was not expected. There exists a script in scripts/ that extracts the relocations from vmlinux that is then used at postlink to check the relocations. Signed-off-by: Alexandre Ghiti <[email protected]> Reviewed-by: Anup Patel <[email protected]>

We should masks all attributes BITS first, and then using '>> _PAGE_PFN_SHIFT' to get the final PFN value. Adding '& _PAGE_CHG_MASK' makes the code semantics more accurate. Signed-off-by: Guo Ren <[email protected]> Signed-off-by: Liu Shaohua <[email protected]> Cc: Anup Patel <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: Chen-Yu Tsai <[email protected]> Cc: Christoph Hellwig <[email protected]> Cc: Drew Fustini <[email protected]> Cc: Maxime Ripard <[email protected]> Cc: Palmer Dabbelt <[email protected]> Cc: Wei Fu <[email protected]> Cc: Wei Wu <[email protected]>

Some RISC-V CPU vendors have defined their own PTE attributes to solve non-coherent DMA bus problems. That makes _P/SXXX definitions contain global variables which could be initialized at the early boot stage before setup_vm. This patch is similar to 316d097 (x86/pti: Filter at vma->vm_page_prot population) which give a choice for arch custom implementation. Signed-off-by: Guo Ren <[email protected]> Cc: Andrew Morton <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: Palmer Dabbelt <[email protected]>

The dma-noncoherent SOCs need different virtual memory mappings with different attributes: - noncached + Strong Order (for IO/DMA descriptor) - noncached + Weak Order (for writecombine usage, eg: frame buffer) All above base on PTE attributes by MMU hardware. That means address attributes are determined by PTE entry, not PMA. RISC-V soc vendors have defined their own custom PTE attributes for dma-noncoherency. Signed-off-by: Guo Ren <[email protected]> Signed-off-by: Liu Shaohua <[email protected]> Cc: Palmer Dabbelt <[email protected]> Cc: Christoph Hellwig <[email protected]> Cc: Anup Patel <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: Drew Fustini <[email protected]> Cc: Wei Fu <[email protected]> Cc: Wei Wu <[email protected]> Cc: Chen-Yu Tsai <[email protected]> Cc: Maxime Ripard <[email protected]>

To support DMA device in a non-coherent interconnect SOC system, we need the below facilities: - Changing a virtual memory mapping region attributes from cacheable to noncache + strong order which used in DMA descriptors. - Add noncache + weakorder virtual memory attributes for dma mapping. - Syncing the cache with memory before DMA start and after DMA end with vendor custom CMO instructions. This patch enables linux kernel generic dma-noncoherency infrastructure and introduces new sbi_ecall API for dma_sync. @@ -27,6 +27,7 @@ enum sbi_ext_id { + SBI_EXT_DMA = 0xAB150401, Signed-off-by: Guo Ren <[email protected]> Signed-off-by: Liu Shaohua <[email protected]> Cc: Palmer Dabbelt <[email protected]> Cc: Christoph Hellwig <[email protected]> Cc: Anup Patel <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: Drew Fustini <[email protected]> Cc: Wei Fu <[email protected]> Cc: Wei Wu <[email protected]> Cc: Chen-Yu Tsai <[email protected]> Cc: Maxime Ripard <[email protected]>

It's a draft version to show you how T-HEAD C9xx work with the icache sync (We use hardware broadcast mechanism, and our icache is VIPT): - icache.i(v/p)a will broadcast all harts' icache invalidtion - sync.is will broadcast all harts' pipeline flush and ensure all broadcasts finished. This patch could improve the performance of OpenJDK on JIT and reduce flush_icache_all in linux. Epecially: static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval) { if (pte_present(pteval) && pte_exec(pteval)) flush_icache_pte(pteval); set_pte(ptep, pteval); } Different from sbi_dma_sync, it can't be hidden in SBI and we must set up a framework to hold all vendors' implementations in linux/arch/riscv. Signed-off-by: Guo Ren <[email protected]> Signed-off-by: Liu Shaohua <[email protected]> Cc: Anup Patel <[email protected]> Cc: Atish Patra <[email protected]> Cc: Palmer Dabbelt <[email protected]> Cc: Chen-Yu Tsai <[email protected]> Cc: Drew Fustini <[email protected]> Cc: Maxime Ripard <[email protected]> Cc: Palmer Dabbelt <[email protected]> Cc: Wei Fu <[email protected]> Cc: Wei Wu <[email protected]>

Signed-off-by: Samuel Holland <[email protected]>

It's better to use efuse_xlate to extract the differentiated part regarding different SoC. Signed-off-by: Shuosheng Huang <[email protected]> Signed-off-by: Samuel Holland <[email protected]>

Add nvmem based cpufreq for Allwinner A100 SoC, which is similar to H6. Signed-off-by: Shuosheng Huang <[email protected]> Signed-off-by: Samuel Holland <[email protected]>

Signed-off-by: Samuel Holland <[email protected]>

The Allwinner D1 SoC has a crypto engine compatible with sun8i-ce. Add support for it. Signed-off-by: Corentin Labbe <[email protected]> Signed-off-by: Samuel Holland <[email protected]>

Signed-off-by: Samuel Holland <[email protected]>

As Icenowy pointed out, newer manuals (starting with H6) actually document the register block at offset 0x800 as "HCI controller and PHY interface", also describe the bits in our "PMU_UNK1" register. Let's put proper names to those "unknown" variables and symbols. While we are at it, generalise the existing code by allowing a bitmap of bits to clear and set, to cover newer SoCs: The A100 and H616 use a different bit for the SIDDQ control. Signed-off-by: Andre Przywara <[email protected]>

Signed-off-by: Samuel Holland <[email protected]>

This adds binding documentation for sun8i-v536 SoC PWM driver. Signed-off-by: Ban Tao <[email protected]>

The Allwinner R818, A133, R329, V536 and V833 has a new PWM controller IP compared to the older Allwinner SoCs. Signed-off-by: Ban Tao <[email protected]>

Signed-off-by: Samuel Holland <[email protected]>

Newer versions of the Allwinner RTC, as for instance found in the H616 SoC, no longer store a broken-down day/month/year representation in the RTC_DAY_REG, but just a linear day number. The user manual does not give any indication about the expected epoch time of this day count, but the BSP kernel uses the UNIX epoch, which allows easy support due to existing conversion functions in the kernel. Allow tagging a compatible string with a flag, and use that to mark those new RTCs. Then convert between a UNIX day number (converted into seconds) and the broken-down day representation using mktime64() and time64_to_tm() in the set_time/get_time functions. That enables support for the RTC in those new chips. Reviewed-by: Andre Przywara <[email protected]>

The H616 RTC changes its day storage to the newly introduced linear day scheme, so pair the new compatible string with this feature flag. So far the clock parts seem to be the same as the H6, so combine the compatible string with the existing H6 support bits. Signed-off-by: Andre Przywara <[email protected]>

This doesn't work, but it is good enough to let clock consumers probe. Signed-off-by: Samuel Holland <[email protected]>

Signed-off-by: Samuel Holland <[email protected]>

Avoid a build warning drivers/pinctrl/sunxi/pinctrl-sunxi.c: In function ‘sunxi_pinctrl_irq_ack’: drivers/pinctrl/sunxi/pinctrl-sunxi.c:1035:2: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement] 1035 | u32 new = readl(pctl->membase + status_reg); | ^~~ Signed-off-by: Heinrich Schuchardt <[email protected]>

This reverts commit e635dfa.

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Upgrade to v5.14 and some fixes #2

Upgrade to v5.14 and some fixes #2

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