Replace the OVMF-specific SataControllerDxe (to be later removed) with
the generic, MdeModulePkg one, for the Bhyve platform.

Signed-off-by: Pedro Falcato <[email protected]>
Acked-by: Gerd Hoffmann <[email protected]>
Acked-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Laszlo Ersek <[email protected]>
Acked-by: Peter Grehan <[email protected]>
Acked-by: Corvin Köhne <[email protected]>

Replace the OVMF-specific SataControllerDxe (to be later removed) with
the generic, MdeModulePkg one, for the CloudHv platform.

Signed-off-by: Pedro Falcato <[email protected]>
Acked-by: Ard Biesheuvel <[email protected]>
Acked-by: Gerd Hoffmann <[email protected]>

Replace the OVMF-specific SataControllerDxe (to be later removed) with
the generic, MdeModulePkg one, for the IntelTdx platform.

Signed-off-by: Pedro Falcato <[email protected]>
Acked-by: Gerd Hoffmann <[email protected]>
Acked-by: Ard Biesheuvel <[email protected]>

Replace the OVMF-specific SataControllerDxe (to be later removed) with
the generic, MdeModulePkg one, for the AmdSev platform.

Signed-off-by: Pedro Falcato <[email protected]>
Acked-by: Ard Biesheuvel <[email protected]>
Acked-by: Gerd Hoffmann <[email protected]>

Replace the OVMF-specific SataControllerDxe (to be later removed) with
the generic, MdeModulePkg one, for the OvmfXen platform.

Signed-off-by: Pedro Falcato <[email protected]>
Acked-by: Gerd Hoffmann <[email protected]>
Acked-by: Ard Biesheuvel <[email protected]>
Acked-by: Anthony PERARD <[email protected]>

Now that OvmfPkg/SataControllerDxe and its MdeModulePkg counterpart have
been unified, and no in-tree uses of the OVMF variant remain, let's
delete it.

Tested-by: Gerd Hoffmann <[email protected]>
Acked-by: Gerd Hoffmann <[email protected]>
Signed-off-by: Pedro Falcato <[email protected]>
Acked-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Laszlo Ersek <[email protected]>

…view.

As per the SMBIOS spec, in smbios type0 table, if the Bios size is
greater than 16MB, extended bios size is used to update size information
and bios size is set to 0xff. when this data is printed by smbiosview,
both bios size and extended bios size is printed if the smbios version
is beyond 3.1, which is incorrect as Bios size is set to 0xff when
rom size is more than 16MB.

To fix this bug, added a condition to print bios size only when it is
not set to 0xff or if the smbios version is older than 3.1.

Signed-off-by: Thejaswani Putta <[email protected]>
Cc: Ray Ni <[email protected]>
Cc: Zhichao Gao <[email protected]>
Reviewed-by: Zhichao Gao <[email protected]>

In case ShellConvertStringToUint64() fails the Handles are left
uninitialized.  That can for example happen for Handle2 and Handle3 in
case only one parameter was specified on the command line. Which can
trigger the ASSERT() in line 185.

Reproducer: boot ovmf to efi shell in qemu, using q35 machine type, then
try disconnect the sata controller in efi shell.

Fix that by explicitly setting them to NULL in that case.  While being
at it also simplify the logic and avoid pointlessly calling
ShellConvertStringToUint64() in case ParamN is NULL.

Signed-off-by: Gerd Hoffmann <[email protected]>
Reviewed-by: Zhichao Gao <[email protected]>

Uncrustify checks are too rigid, making them counter-productive:

- it leads to code that is arguably harder to parse visually (e.g.,
  the changes to ArmPkg/Include/Chipset/AArch64Mmu.h in commit
  429309e)
- it forces indentation-only changes to code in the vicinity of actual
  changes, making the code history more bloated than necessary (see
  commit 7f19832 for an example)
- finding out from the web UI what exactly Uncrustify objected to is not
  straight-forward.

So let's enable AuditMode for ArmPkg, so that interested parties can see
the uncrustify recommendations if desired, but without preventing the
changes from being merged. This leaves it at the discretion of the
ArmPkg maintainers to decide which level of conformance is required.

Cc: Leif Lindholm <[email protected]>
Cc: "Kinney, Michael D" <[email protected]>
Cc: Michael Kubacki <[email protected]>
Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Leif Lindholm <[email protected]>

They are useful for those platforms where SMC SiP calls exist.

Signed-off-by: Marcin Juszkiewicz <[email protected]>
Reviewed-by: Leif Lindholm <[email protected]>

The RISC-V version of the DXE IPL does not implement setting the stack
NX, so before switching to an implementation that will ASSERT() on the
missing support, drop the PCD setting that enables it.

Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Sunil V L <[email protected]>

Edk2 was failing, rather than creating more PML4 entries, when they
weren't present in the initial memory acceptance flow. Because of that
VMs with more than 512G memory were crashing. This code fixes that.

This change affects only SEV-SNP VMs.

The code was tested by successfully booting a 512G SEV-SNP VM.

Signed-off-by: Mikolaj Lisik <[email protected]>
Acked-by: Gerd Hoffmann <[email protected]>
Acked-by: Tom Lendacky <[email protected]>

Xen and bhyve are placing ACPI tables into system memory. So, they can
share the same code. Therefore, create a new library which searches and
installs ACPI tables from system memory.

Signed-off-by: Corvin Köhne <[email protected]>
Reviewed-by: Anthony PERARD <[email protected]>
Acked-by: Gerd Hoffmann <[email protected]>

This makes the function reuseable by bhyve.

Signed-off-by: Corvin Köhne <[email protected]>
Reviewed-by: Anthony PERARD <[email protected]>
Acked-by: Gerd Hoffmann <[email protected]>

It's much easier to create configuration dependent ACPI tables for bhyve
than for OVMF. For this reason, don't use the statically created ACPI
tables provided by OVMF. Instead, prefer the dynamically created ACPI
tables of bhyve. If bhyve provides no ACPI tables or we are unable to
detect those, fall back to OVMF tables.

Ideally, we use the qemu fwcfg interface to pass the ACPI tables from
bhyve to OVMF. bhyve will support this in the future. However, current
bhyve executables don't support passing ACPI tables by the qemu fwcfg
interface. They just copy the ACPI into main memory. For that reason,
pick up the ACPI tables from main memory.

Signed-off-by: Corvin Köhne <[email protected]>
Reviewed-by: Rebecca Cran <[email protected]>
Acked-by: Peter Grehan <[email protected]>
Acked-by: Gerd Hoffmann <[email protected]>

Currently, CharEncodingCheckPlugin prints a message for every
file that passes the test, which for some platforms can cause
most of the CI build log to be filled with this print. It does
not add any value, so this patch removes the noisy print and
only prints if the encoding check fails.

Cc: Sean Brogan <[email protected]>
Cc: Michael Kubacki <[email protected]>
Cc: Michael D Kinney <[email protected]>
Cc: Liming Gao <[email protected]>
Reviewed-by: Michael D Kinney <[email protected]>
Reviewed-by: Michael Kubacki <[email protected]>
Signed-off-by: Oliver Smith-Denny <[email protected]>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4474

ACPI_Spec_6_5_Aug29 Table 5.19 page 128 that MADT Revision
field is 6.

Cc: Michael D Kinney <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Zhiguang Liu <[email protected]>
Cc: Jiewen Yao <[email protected]>
Signed-off-by: Aryeh Chen <[email protected]>
Reviewed-by: Michael D Kinney <[email protected]>
Reviewed-by: Liming Gao <[email protected]>
Tested-by: Aryeh Chen <[email protected]>

Implement the SpeculationBarrier with implementations consisting of
fence instruction which provides finer-grain memory orderings.
Perform Data Barrier in RiscV: fence rw,rw
Perform Instruction Barrier in RiscV: fence.i; fence r,r
More detail is in Appendix A: RVWMO Explanatory Material in
https://github.com/riscv/riscv-isa-manual

This API is first introduced in the below commits for IA32 and x64
tianocore/edk2@d9f1cac
tianocore/edk2@e83d841
and below the commit for ARM and AArch64 implementation
tianocore/edk2@c0959b4

This commit is to add the RiscV64 implementation which will be used by
variable service under Variable/RuntimeDxe

Cc: Andrei Warkentin <[email protected]>
Cc: Evan Chai <[email protected]>
Cc: Sunil V L <[email protected]>
Cc: Tuan Phan <[email protected]>
Signed-off-by: Yong Li <[email protected]>
Reviewed-by: Sunil V L <[email protected]>

If there is no port multiplier, PortMultiplierPort should be converted
to 0 to follow AHCI spec.
The same logic already applied in AtaAtapiPassThruDxe driver.

Signed-off-by: Neo Hsueh <[email protected]>
Acked-by: Abner Chang <[email protected]>
Reviewed-by: Hao A Wu <[email protected]>

RedfishClientPkg is moved from edk2-staging repository to
edk2-redfish-client repository. Update the link in Readme.md
to new location.

Signed-off-by: Nickle Wang <[email protected]>
Cc: Abner Chang <[email protected]>
Cc: Igor Kulchytskyy <[email protected]>
Reviewed-by: Abner Chang <[email protected]>

Supreeth is no longer [email protected]. Therefore,
remove the reviewer entry from StandaloneMmPkg.

Signed-off-by: Sami Mujawar <[email protected]>

Add Ray, remove Jiewen.

Signed-off-by: Ray Ni <[email protected]>
Reviewed-by: Sami Mujawar <[email protected]>
Reviewed-by: Jiewen Yao <[email protected]>

Currently, have two command for pre-build binary support
1. --BuildEntryOnly: build UPL Entry file
2. --PreBuildUplBinary: build UPL binary based on UPL

And these two commands should be exclusived, shouldn't
have chance run it in the meantime.

Case1: Build UPL entry with CLANGDWARF
  python UefiPayloadPkg/UniversalPayloadBuild.py --BuildEntryOnly

Case2: Use pre-built UPL entry and build other fv by VS2019
  python UefiPayloadPkg/UniversalPayloadBuild.py -t VS2019 \
    --PreBuildUplBinary UniversalPayload.elf

Case3: Build UPL Entry with CLANGDWARF and build other fv by VS2019
  python UefiPayloadPkg/UniversalPayloadBuild.py -t VS2019

Cc: Guo Dong <[email protected]>
Cc: Ray Ni <[email protected]>
Cc: Sean Rhodes <[email protected]>
Cc: James Lu <[email protected]>
Cc: Gua Guo <[email protected]>
Signed-off-by: Gua Guo <[email protected]>
Reviewed-by: James Lu <[email protected]>

The initial version of Smbios Specification 3.6.0
type 45 and type 46 support.

Signed-off-by: Simon Wang <[email protected]>
Cc: Ray Ni <[email protected]>
Cc: Zhichao Gao <[email protected]>
Reviewed-by: Zhichao Gao <[email protected]>

This library supports a PeiServicesTablePointerLib implementation
that allows code dependent upon PeiServicesTable to operate in an
isolated execution environment such as within the context of a
host-based unit test framework.

The unit test should initialize the PeiServicesTable database with
any required elements (e.g. PPIs, Hob etc.) prior to the services
being invoked by code under test.

It is strongly recommended to clean any global databases by using
EFI_PEI_SERVICES.ResetSystem2 after every unit test so the tests
execute in a predictable manner from a clean state.

Cc: Michael D Kinney <[email protected]>
Reviewed-by: Michael Kubacki <[email protected]>
Cc: Sean Brogan <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Signed-off-by: Zhiguang Liu <[email protected]>

The Shell binaries are not generated anymore in each
stable tag release.
So, remove the section.

Reviewed-by: Zhichao Gao <[email protected]>
Cc: Leif Lindholm <[email protected]>
Reviewed-by: Ard Biesheuvel <[email protected]>
Signed-off-by: Ray Ni <[email protected]>

Signed-off-by: Ray Ni <[email protected]>
Cc: Guo Dong <[email protected]>
Cc: Sean Rhodes <[email protected]>
Cc: James Lu <[email protected]>
Reviewed-by: Gua Guo <[email protected]>
Reviewed-by: Zhichao Gao <[email protected]>
Reviewed-by: Gua Guo <[email protected]>

…ault

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4479

Add CAPSULE_SUPPORT to optionally select CapsuleLib instance,
default value is FALSE.

Cc: Ray Ni <[email protected]>
Cc: Sean Rhodes <[email protected]>
Reviewed-by: Gua Guo <[email protected]>
Reviewed-by: James Lu <[email protected]>
Cc: Guo Dong <[email protected]>

Signed-off-by: MarsX Lin <[email protected]>

Fix incorrect code on AddSectionHeader32() and AddSectionHeader64()

Cc: Guo Dong <[email protected]>
Cc: Sean Rhodes <[email protected]>
Cc: James Lu <[email protected]>
Cc: Gua Guo <[email protected]>
Signed-off-by: BruceX Wang <[email protected]>
Reviewed-by: Gua Guo <[email protected]>

SbiSetTimer expects core tick value.

Cc: Andrei Warkentin <[email protected]>
Signed-off-by: Tuan Phan <[email protected]>
Reviewed-by: Sunil V L <[email protected]>

The timer compare register is 64-bit so simplifying the delay
function.

Cc: Andrei Warkentin <[email protected]>
Signed-off-by: Tuan Phan <[email protected]>
Reviewed-by: Sunil V L <[email protected]>

Cc: Jiewen Yao <[email protected]> [jyao1]
Cc: Yi Li <[email protected]> [liyi77]
Cc: Xiaoyu Lu <[email protected]> [xiaoyuxlu]
Cc: Guomin Jiang <[email protected]> [guominjia]
Signed-off-by: Jian J Wang <[email protected]>
Reviewed-by: [email protected]
Reviewed-by: Yi Li <[email protected]>

The patch adds perf-logging for the following potential
time-consuming BSP procedures:
* PiCpuSmmEntry
  - SmmRelocateBases
  - ExecuteFirstSmiInit

* BSPHandler
  - SmmWaitForApArrival
  - PerformRemainingTasks
    * InitPaging
    * SetMemMapAttributes
    * SetUefiMemMapAttributes
    * SetPageTableAttributes
    * ConfigSmmCodeAccessCheck
    * SmmCpuFeaturesCompleteSmmReadyToLock

Signed-off-by: Ray Ni <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>
Reviewed-by: Jiaxin Wu <[email protected]>
Reviewed-by: Eric Dong <[email protected]>

MP procedures are those procedures that run in every CPU thread.
The EDKII perf infra is not MP safe so it doesn't support to be called
from those MP procedures.

The patch adds SMM MP perf-logging support in SmmMpPerf.c.
The following procedures are perf-logged:
* SmmInitHandler
* SmmCpuFeaturesRendezvousEntry
* PlatformValidSmi
* SmmCpuFeaturesRendezvousExit

Signed-off-by: Ray Ni <[email protected]>
Cc: Eric Dong <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>
Cc: Jiaxin Wu <[email protected]>
Reviewed-by: Jiaxin Wu <[email protected]>
Reviewed-by: Eric Dong <[email protected]>

Following procedures are perf-logged:
* SmmReadyToBootHandler
* SmmReadyToLockHandler
* SmmEndOfDxeHandler
* SmmEntryPoint
  (It's the main routine run in BSP when SMI happens.)
* SmiManage

Signed-off-by: Ray Ni <[email protected]>
Cc: Jian J Wang <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Jiaxin Wu <[email protected]>
Reviewed-by: Jiaxin Wu <[email protected]>
Reviewed-by: Eric Dong <[email protected]>
Reviewed-by: Jian J Wang <[email protected]>

SmmDriverDispatchHandler is the routine that dispatches SMM drivers
from FV. It's a time-consuming routine.
Add perf-logging for this routine.

Signed-off-by: Ray Ni <[email protected]>
Cc: Jian J Wang <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Jiaxin Wu <[email protected]>
Reviewed-by: Jiaxin Wu <[email protected]>
Reviewed-by: Eric Dong <[email protected]>
Reviewed-by: Jian J Wang <[email protected]>

Because SMM perf-logging is migrated to non-SMRAM at ReadyToBoot
by DxeCorePerformanceLib, the perf-logging after ExitBS is useless and
impact the SMI latency at runtime.
Hence the SmmPerformanceLib is updated to disable perf-logging
after ExitBS.

Signed-off-by: Ray Ni <[email protected]>
Cc: Jiaxin Wu <[email protected]>
Cc: Dandan Bi <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Jian J Wang <[email protected]>
Reviewed-by: Jiaxin Wu <[email protected]>
Reviewed-by: Eric Dong <[email protected]>
Reviewed-by: Jian J Wang <[email protected]>

Because SMM perf-logging is migrated to non-SMRAM at ReadyToBoot
by DxeCorePerformanceLib, the perf-logging after ExitBS is useless and
impact the SMI latency at runtime.
Hence the SmmCorePerformanceLib is updated to disable perf-logging
after ExitBS.

Signed-off-by: Ray Ni <[email protected]>
Cc: Jiaxin Wu <[email protected]>
Cc: Dandan Bi <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Jian J Wang <[email protected]>
Reviewed-by: Jiaxin Wu <[email protected]>
Reviewed-by: Eric Dong <[email protected]>
Reviewed-by: Jian J Wang <[email protected]>

When a platform has lots of CPU cores/threads, perf-logging on every
AP produces lots of records. When this multiplies with number of SMIs
during post, the records are even more.

So, this patch adds a new PCD PcdSmmApPerfLogEnable (default TRUE)
to allow platform to turn off perf-logging on APs.

Signed-off-by: Ray Ni <[email protected]>
Cc: Eric Dong <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>
Reviewed-by: Jiaxin Wu <[email protected]>
Reviewed-by: Eric Dong <[email protected]>

Signed-off-by: Ray Ni <[email protected]>
Cc: Jian J Wang <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Jiaxin Wu <[email protected]>
Reviewed-by: Jian J Wang <[email protected]>

This commit is code optimization to InternalAllocateAlignedPages of
SmmMemoryAllocationLib which can reduce free memory fragments. Also
it can reduce one pre-allocation page.

Let's take a simple example:
The expected pages size is 8KB, Alignment value is 8KB.

In original InternalAllocateAlignedPages(), the first step is to
allocate 4 pages and then find the first 8KB-aligned address in
allocated 4 pages. If the upper limit address of allocated 4 pages
is already 8KB aligned, then the allocated 4 pages contains two
8KB-aligned 8KB ranges. The lower 2 pages will be selected and
removed from free pages. Then the higher 2 pages will be free.
Since the whole memory allocation is from high address to low
address, then the higher 2 pages cann't be merged with other free
pages, causing the free memory fragments.

However, when only allocate 3(2+2-1) pages, we can avoid the free
memory fragments in specific case. Also 3 pages must contain a
8KB-aligned 8KB range, which meets the requirement. If the upper
limit address of allocated 3 pages is 8KB-aligned, then the higher
2 pages range of allocated 3 pages is 8KB-aligned and will be
selected and removed from free pages. The remaining lower one page
of allocated 3 pages will be free and merged with left lower free
memory. This can reduce free memory fragments in smm.

Signed-off-by: Dun Tan <[email protected]>
Cc: Ray Ni <[email protected]>
Reviewed-by: Michael D Kinney <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Zhiguang Liu <[email protected]>

The size of the FV and the WriteQueueSize is incorrect which causes
the flash to be re-written during boot. Fix them and update the new
checksum value.

Signed-off-by: Sunil V L <[email protected]>
Cc: Ard Biesheuvel <[email protected]>
Cc: Jiewen Yao <[email protected]>
Cc: Jordan Justen <[email protected]>
Cc: Gerd Hoffmann <[email protected]>
Cc: Andrei Warkentin <[email protected]>
Cc: Heinrich Schuchardt <[email protected]>

This library is required to support separate code and
variable store images.

Signed-off-by: Sunil V L <[email protected]>
Cc: Ard Biesheuvel <[email protected]>
Cc: Jiewen Yao <[email protected]>
Cc: Jordan Justen <[email protected]>
Cc: Gerd Hoffmann <[email protected]>
Cc: Andrei Warkentin <[email protected]>
Cc: Heinrich Schuchardt <[email protected]>

Currently, RiscVVirtQemu supports unified code and variable store
mainly because only one pflash devices was available in qemu for
EDK2. However, this doesn't allow to map the code part as read-only.

With recent qemu enhancements, it is now possible for EDK2 to make
use of both pflash devices in RISC-V virt machine. So, add support
to create code and vars images separately. This also allows easy
firmware code updates without losing the variable store.

Signed-off-by: Sunil V L <[email protected]>
Cc: Ard Biesheuvel <[email protected]>
Cc: Jiewen Yao <[email protected]>
Cc: Jordan Justen <[email protected]>
Cc: Gerd Hoffmann <[email protected]>
Cc: Andrei Warkentin <[email protected]>
Cc: Heinrich Schuchardt <[email protected]>

Add a readme file which provides information regarding how
to build and test EDK2 on RISC-V qemu virt platform.

Signed-off-by: Sunil V L <[email protected]>
Cc: Ard Biesheuvel <[email protected]>
Cc: Jiewen Yao <[email protected]>
Cc: Jordan Justen <[email protected]>
Cc: Gerd Hoffmann <[email protected]>
Cc: Andrei Warkentin <[email protected]>
Cc: Heinrich Schuchardt <[email protected]>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3794

This change introduces a new error code definitions under Host Software
class according to PI specification v1.8.

The new error code definition will cover system reboot events under the
conditions of inconsistent memory map from one boot to another.

These error codes could provide helpful datapoints to OEMs to investigate
and prevent system failures in general.

Cc: Michael D Kinney <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Zhiguang Liu <[email protected]>

Signed-off-by: Kun Qin <[email protected]>
Reviewed-by: Liming Gao <[email protected]>
Reviewed-by: Michael D Kinney <[email protected]>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3966

This change introduces a new peripheral subclass definition from PI
specification v1.8.

The new subclass definition will cover system reboot events under the
status reports from Trusted Platform Modules (TPMs).

These definition could provide helpful datapoints to OEMs to analyze
system security state and healthiness, as well as avoid definition
collision with other existing peripheral subclass definitions.

Cc: Michael D Kinney <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Zhiguang Liu <[email protected]>

Signed-off-by: Kun Qin <[email protected]>
Reviewed-by: Liming Gao <[email protected]>
Reviewed-by: Michael D Kinney <[email protected]>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3966

This change updated the default value of TPM device subclass PCD to
`0x010E0000` in order to match the definition of EFI_PERIPHERAL_TPM
from PI specification v1.8.

Cc: Jiewen Yao <[email protected]>
Cc: Jian J Wang <[email protected]>
Cc: Qi Zhang <[email protected]>
Cc: Rahul Kumar <[email protected]>

Signed-off-by: Kun Qin <[email protected]>
Reviewed-by: Jiewen Yao <[email protected]>
Reviewed-by: Liming Gao <[email protected]>
Reviewed-by: Michael D Kinney <[email protected]>

The definition and declaration of GetAcpiRsdpFromMemory doesn't match.
We don't get a compile error yet because UINTN is the same as UINT64 on
64bit machines. As the function works on memory addresses, UINTN is the
correct type of the input parameters.

Signed-off-by: Corvin Köhne <[email protected]>
Tested-by: Gerd Hoffmann <[email protected]>
Acked-by: Gerd Hoffmann <[email protected]>
Acked-by: Peter Grehan <[email protected]>

Signed-off-by: Corvin Köhne <[email protected]>
Acked-by: Peter Grehan <[email protected]>

Bhyve supports providing ACPI tables by FwCfg. Therefore,
InstallQemuFwCfgTables should be moved to AcpiPlatformLib to reuse the
code. As first step, move PciEncoding into AcpiPlatformLib.

Signed-off-by: Corvin Köhne <[email protected]>
Acked-by: Peter Grehan <[email protected]>

This is required to move InstallQemuFwCfgTables into AcpiPlatformLib.

Signed-off-by: Corvin Köhne <[email protected]>
Acked-by: Peter Grehan <[email protected]>

This makes the InstallQemuFwcfgTables function reusable by bhyve.

Signed-off-by: Corvin Köhne <[email protected]>
Acked-by: Peter Grehan <[email protected]>

Signed-off-by: Corvin Köhne <[email protected]>
Acked-by: Peter Grehan <[email protected]>

Bhyve will gain support for TPM emulation in the near future. Therefore,
prepare OVMF by copying all TPM driver used by qemu's OVMF DSC into the
bhyve OVMF DSC.

Signed-off-by: Corvin Köhne <[email protected]>
Reviewed-by: Rebecca Cran <[email protected]>
Acked-by: Gerd Hoffmann <[email protected]>

REF : https://bugzilla.tianocore.org/show_bug.cgi?id=4480

In the FspsWrapperPeim, before calling FspWrapperVariableRequestHandler
and FspWrapperMultiPhaseHandler ,FspHobListPtr should be available so
that BL will be able to get the correct FspHobListPtr value

Signed-off-by: kurugodx <[email protected]>
Cc: Chasel Chiu <[email protected]>
Cc: Nate DeSimone <[email protected]>
Cc: Duggapu Chinni B <[email protected]>
Cc: Chen Gang C <[email protected]>
Cc: Star Zeng <[email protected]>
Cc: Ted Kuo <[email protected]>
Cc: Ashraf Ali S <[email protected]>
Cc: Susovan Mohapatra <[email protected]>
Reviewed-by: Ashraf Ali S <[email protected]>
Reviewed-by: Chasel Chiu <[email protected]>

Define a PPI interface that may be used by the PEI core or other PEIMs
to manage permissions on memory ranges. This is primarily intended for
restricting permissions to what is actually needed for correct execution
by the code in question, and for limiting the use of memory mappings
that are both writable and executable at the same time.

Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Oliver Smith-Denny <[email protected]>
Reviewed-by: Michael Kubacki <[email protected]>
Reviewed-by: Liming Gao <[email protected]>

The Risc-V and LoongArch specific versions of the DXE core handoff code
in DxeIpl are essentially copies of the EBC version (modulo the
copyright in the header and some debug prints in the code).

In preparation for introducing a generic PPI based method to implement
the non-executable stack, let's merge these versions, so we only need to
add this logic once.

Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Oliver Smith-Denny <[email protected]>
Reviewed-by: Michael Kubacki <[email protected]>
Reviewed-by: Liming Gao <[email protected]>

If the associated PCD is set to TRUE, use the memory attribute PPI to
remap the stack non-executable. This provides a generic method for doing
so, which will be used by ARM and AArch64 as well once they move to the
generic DxeIpl handoff implementation.

Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Oliver Smith-Denny <[email protected]>
Reviewed-by: Michael Kubacki <[email protected]>
Reviewed-by: Liming Gao <[email protected]>

Currently, ArmSetMemoryAttributes () takes a combination of
EFI_MEMORY_xx constants describing the memory type and permission
attributes that should be set on a region of memory. In cases where the
memory type is omitted, we assume that the memory permissions being set
are final, and that existing memory permissions can be discarded.

This is problematic, because we aim to map memory non-executable
(EFI_MEMORY_XP) by default, and only relax this requirement for code
regions that are mapped read-only (EFI_MEMORY_RO). Currently, setting
one permission clears the other, and so code managing these permissions
has to be aware of the existing permissions in order to be able to
preserve them, and this is not always tractable (e.g., the UEFI memory
attribute protocol implements an abstraction that promises to preserve
memory permissions that it is not operating on explicitly).

So let's add an AttributeMask parameter to ArmSetMemoryAttributes(),
which is permitted to be non-zero if no memory type is being provided,
in which case only memory permission attributes covered in the mask will
be affected by the update.

Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Oliver Smith-Denny <[email protected]>
Reviewed-by: Michael Kubacki <[email protected]>

Implement the newly defined PPI that permits the PEI core and DXE IPL to
manage memory permissions on ranges of DRAM, for doing things like
mapping the stack non-executable, or granting executable permissions to
shadowed PEIMs.

Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Oliver Smith-Denny <[email protected]>
Reviewed-by: Michael Kubacki <[email protected]>

Now that we have a generic method to manage memory permissions using a
PPI, we can switch to the generic version of the DXE handoff code in
DxeIpl, and drop the ARM specific version.

Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Oliver Smith-Denny <[email protected]>
Reviewed-by: Michael Kubacki <[email protected]>
Reviewed-by: Liming Gao <[email protected]>

Now that ArmSetMemoryAttributes() permits a mask to be provided, we can
simplify the implementation the UEFI memory attribute protocol
substantially, and just pass on the requested mask to be set or cleared
directly.

Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Oliver Smith-Denny <[email protected]>
Reviewed-by: Michael Kubacki <[email protected]>

Smallest IO window size for PCI bridges is 0x1000.  Fix default size
accordingly.  Avoids broken resource assignments like this:

    [ ... ]
    PciBus: Resource Map for Root Bridge PciRoot(0x0)
    Type =   Io16; Base = 0x6000;   Length = 0x7000;        Alignment = 0xFFF
    [ ... ]
       Base = 0xC000;       Length = 0x200; Alignment = 0xFFF;      Owner = PPB [00|02|00:**]
       Base = 0xC200;       Length = 0x40;  Alignment = 0x3F;       Owner = PCI [00|1F|03:20]
       Base = 0xC240;       Length = 0x20;  Alignment = 0x1F;       Owner = PCI [00|1F|02:20]
    [ ... ]

... which the linux kernel fixes up later:

    [    0.644657] pci 0000:00:1f.3: BAR 4: assigned [io  0x1000-0x103f]
    [    0.646833] pci 0000:00:1f.2: BAR 4: assigned [io  0x1040-0x105f]

With the patch applied:

    { ... ]
    PciBus: Resource Map for Root Bridge PciRoot(0x0)
    Type =   Io16; Base = 0x6000;   Length = 0x8000;        Alignment = 0xFFF
    [ ... ]
       Base = 0xC000;       Length = 0x1000;        Alignment = 0xFFF;      Owner = PPB [00|02|00:**]
       Base = 0xD000;       Length = 0x40;  Alignment = 0x3F;       Owner = PCI [00|1F|03:20]
       Base = 0xD040;       Length = 0x20;  Alignment = 0x1F;       Owner = PCI [00|1F|02:20]
    [ ... ]

Signed-off-by: Gerd Hoffmann <[email protected]>

Use the latest Linux container image (from 2023-05-30).
It uses Qemu 8.0.0 and gcc 12.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4324

Signed-off-by: Oliver Steffen <[email protected]>
Acked-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Michael Kubacki <[email protected]>

Since ResetVector source module shares the same GUID as the binary
module, the binary INF file is just removed from DSC.

Signed-off-by: Ray Ni <[email protected]>
Reviewed-by: Eric Dong <[email protected]>
Cc: Rahul Kumar <[email protected]>
Acked-by: Gerd Hoffmann <[email protected]>

ResetVector assembly implementation puts "ALIGN 16" in the end
to guarantee the final executable file size is multiple of 16 bytes.
Because the module uses a special GUID which guarantees it's put in
the very end of a FV, which should be also the end of the FD.
All of these (file size is multiple of 16B, and the module is put at
end of FV, FV is put at end of FD) guarantee the "JMP xxx" instruction
is at FFFF_FFF0h.

This patch updates INF file and ReadMe.txt to add guidance of FDF ffs
rule for the ResetVector.

Signed-off-by: Ray Ni <[email protected]>
Reviewed-by: Eric Dong <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>
Acked-by: Gerd Hoffmann <[email protected]>

Because it's simpler for a platform to include the ResetVector source
and having pre-built binaries add burdens of updating the pre-built
binaries. This patch removes the pre-built binaries and the script
that buids the pre-built binaries.

Signed-off-by: Ray Ni <[email protected]>
Reviewed-by: Eric Dong <[email protected]>
Cc: Rahul Kumar <[email protected]>
Acked-by: Gerd Hoffmann <[email protected]>

StandaloneMm has its own version of the ArmMmuLib library class, but
includes the ArmMmuLib header. This happens to work because the
prototypes that are referenced are the same, but this will no longer be
the case after a future patch. So correct the #includes.

Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Leif Lindholm <[email protected]>

Now that we have a sane API to set and clear memory permissions that
works the same on ARM and AArch64, we no longer have a need for the
individual set/clear no-access/read-only/no-exec helpers so let's drop
them.

Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Leif Lindholm <[email protected]>

The OP-TEE secure OS exposes a non-secure memory region for
communication between the secure OS itself and any clients in the
non-secure firmware. This memory is writable by non-secure and is not
used for code only data, and so it should be mapped non-executable.

Signed-off-by: Ard Biesheuvel <[email protected]>
Reviewed-by: Leif Lindholm <[email protected]>

The UEFI driver model invokes the supported() method on every driver
every time a connection attempt is made on any handle, and so doing an
unconditional DEBUG() print inside this method produced a lot of noise.

So let's drop this DEBUG() call from the VirtioSerial driver's
Supported() method.

Signed-off-by: Ard Biesheuvel <[email protected]>
Acked-by: Gerd Hoffmann <[email protected]>

gcc-13 for RISC-V enables unwind tables by default similar to ARM64.
This generates .eh_frame_hdr section which is not handled well by
GenFw causing failures.

Disable the unwind tables by adding -fno-unwind-tables flag similar
to [1].

[1] - tianocore/edk2@cbf00651eda6

Signed-off-by: Sunil V L <[email protected]>
Cc: Rebecca Cran <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Bob Feng <[email protected]>
Cc: Yuwei Chen <[email protected]>
Cc: Andrei Warkentin <[email protected]>
Reviewed-by: Liming Gao <[email protected]>
Reviewed-by: Rebecca Cran <[email protected]>

Add Zack, Saloni and remove unused IDs

Cc: Michael D Kinney <[email protected]>
Cc: Andrew Fish <[email protected]>
Cc: Leif Lindholm <[email protected]>
Cc: Zachary Clark-willilams <[email protected]>
Signed-off-by: Saloni Kasbekar <[email protected]>
Reviewed-by: Zachary Clark-willilams <[email protected]>
Reviewed-by: Michael D Kinney <[email protected]>

FIX: https://bugzilla.tianocore.org/show_bug.cgi?id=4477

Tls connection fail over WiFi in AMT OCR flow due to invalid identity.

This was due to missing conversion between unicode and ascii
string which resulted in invalid strlen.

Cc: Maciej Rabeda <[email protected]>
Cc: Zachary Clark-Williams <[email protected]>
Signed-off-by: Yi Li <[email protected]>
Reviewed-by: Zachary Clark-Williams <[email protected]>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4464

This change introduced the MM communicate support in PEI phase for ARM
based platforms. Similar to the DXE counterpart, `PcdMmBufferBase` is
used as communicate buffer and SMC will be invoked to communicate to
TrustZone when MMI is requested.

Cc: Leif Lindholm <[email protected]>
Cc: Ard Biesheuvel <[email protected]>
Cc: Sami Mujawar <[email protected]>

Co-authored-by: Ronny Hansen <[email protected]>
Co-authored-by: Shriram Masanamuthu Chinnathurai <[email protected]>
Co-authored-by: Preshit Harlikar <[email protected]>
Signed-off-by: Kun Qin <[email protected]>
Reviewed-by: Ard Biesheuvel <[email protected]>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4464

This change introduced the Standalone MM based variable read capability
in PEI phase for applicable platforms (such as ARM platforms).

Similar to the x86 counterpart, MM communicate PPI is used to request
variable information from Standalone MM environment.

Cc: Hao A Wu <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Jian J Wang <[email protected]>

Co-authored-by: Ronny Hansen <[email protected]>
Co-authored-by: Shriram Masanamuthu Chinnathurai <[email protected]>
Co-authored-by: Preshit Harlikar <[email protected]>
Signed-off-by: Kun Qin <[email protected]>
Reviewed-by: Liming Gao <[email protected]>

Remove code that sets AddressEncMask for non-leaf entries when
modifing smm page table by MemEncryptSevLib. In FvbServicesSmm
driver, it calls MemEncryptSevClearMmioPageEncMask to clear
AddressEncMask bit in page table for a specific range. In AMD
SEV feature, this AddressEncMask bit in page table is used to
indicate if the memory is guest private memory or shared memory.
But all memory accessed by the hardware page table walker is
treated as encrypted, regardless of whether the encryption bit
is present. So remove the code to set the EncMask bit for smm
non-leaf entries doesn't impact AMD SEV feature.

The reason encryption mask should not be set for non-leaf
entries is because CpuPageTableLib doesn't consume encryption
mask PCD. In PiSmmCpuDxeSmm module, it will use CpuPageTableLib
to modify smm page table in next patch. The encryption mask is
overlapped with the PageTableBaseAddress field of non-leaf page
table entries. If the encryption mask is set for smm non-leaf
page table entries, issue happens when CpuPageTableLib code
use the non-leaf entry PageTableBaseAddress field with the
encryption mask set to find the next level page table.

Signed-off-by: Dun Tan <[email protected]>
Cc: Ard Biesheuvel <[email protected]>
Cc: Jiewen Yao <[email protected]>
Cc: Jordan Justen <[email protected]>
Cc: Gerd Hoffmann <[email protected]>
Reviewed-by: Tom Lendacky <[email protected]>
Reviewed-by: Ray Ni <[email protected]>

In UnsetGuardPage(), before SmmReadyToLock, remove NX and RO
memory attribute protection for guarded page since
EfiConventionalMemory in SMRAM is RW and executable before
SmmReadyToLock. If UnsetGuardPage() happens after SmmReadyToLock,
then apply EFI_MEMORY_XP to the guarded page to make sure
EfiConventionalMemory in SMRAM is NX since EfiConventionalMemory
in SMRAM is marked as NX in PiSmmCpuDxe driver when SmmReadyToLock.

Signed-off-by: Dun Tan <[email protected]>
Cc: Liming Gao <[email protected]>
Cc: Ray Ni <[email protected]>
Reviewed-by: Jian J Wang <[email protected]>
Cc: Ard Biesheuvel <[email protected]>

Simplify the ConvertMemoryPageAttributes API to convert paging
attribute by CpuPageTableLib. In the new API, it calls
PageTableMap() to update the page attributes of a memory range.
With the PageTableMap() API in CpuPageTableLib, we can remove
the complicated page table manipulating code.

Signed-off-by: Dun Tan <[email protected]>
Cc: Eric Dong <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>

In ConvertMemoryPageAttributes() function, when clear RP for a
specific range [BaseAddress, BaseAddress + Length], it means to
set the present bit to 1 and assign default value for other
attributes in page table. The default attributes for the input
specific range are NX disabled and ReadOnly. If there is existing
present range in [BaseAddress, BaseAddress + Length] and the
attributes are not NX disabled or not ReadOnly, then output the
DEBUG message to indicate that the NX and ReadOnly attributes of
the existing present range are modified in the function.

Signed-off-by: Dun Tan <[email protected]>
Cc: Eric Dong <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>

In PiSmmCpuDxeSmm code, SetMemMapAttributes() marks memory ranges
in SmmMemoryAttributesTable to RO/NX. There may exist non-present
range in these memory ranges. Set other attributes for a non-present
range is not permitted in CpuPageTableMapLib. So add code to handle
this case. Only map the present ranges in SmmMemoryAttributesTable
to RO or NX.

Signed-off-by: Dun Tan <[email protected]>
Cc: Eric Dong <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>

Add two functions to disable/enable CR0.WP. These two unctions
will also be used in later commits. This commit doesn't change any
functionality.

Signed-off-by: Dun Tan <[email protected]>
Cc: Eric Dong <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>

Clear CR0.WP before modify smm page table. Currently, there is
an assumption that smm pagetable is always RW before ReadyToLock.
However, when AMD SEV is enabled, FvbServicesSmm driver calls
MemEncryptSevClearMmioPageEncMask to clear AddressEncMask bit
in smm page table for this range:
[PcdOvmfFdBaseAddress,PcdOvmfFdBaseAddress+PcdOvmfFirmwareFdSize]
If page slpit happens in this process, new memory for smm page
table is allocated. Then the newly allocated page table memory
is marked as RO in smm page table in this FvbServicesSmm driver,
which may lead to PF if smm code doesn't clear CR0.WP before
modify smm page table when ReadyToLock.

Signed-off-by: Dun Tan <[email protected]>
Cc: Eric Dong <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>

Extern mSmmShadowStackSize in PiSmmCpuDxeSmm.h and remove
extern for mSmmShadowStackSize in c files to simplify code.

Signed-off-by: Dun Tan <[email protected]>
Cc: Eric Dong <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>

This commit is code refinement to current smm pagetable generation
code. Add a new GenSmmPageTable() API to create smm page table
based on the PageTableMap() API in CpuPageTableLib. Caller only
needs to specify the paging mode and the PhysicalAddressBits to map.
This function can be used to create both IA32 pae paging and X64
5level, 4level paging.

Signed-off-by: Dun Tan <[email protected]>
Cc: Eric Dong <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>

Use GenSmmPageTable() to create both IA32 and X64 Smm S3
page table.

Signed-off-by: Dun Tan <[email protected]>
Cc: Eric Dong <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>

Sort mSmmCpuSmramRanges after get the SMRAM info in
FindSmramInfo() function.

Signed-off-by: Dun Tan <[email protected]>
Cc: Eric Dong <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>

Sort mProtectionMemRange in InitProtectedMemRange() when
ReadyToLock.

Signed-off-by: Dun Tan <[email protected]>
Cc: Eric Dong <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>

This commit is code refinement to current smm runtime InitPaging()
page table update code. In InitPaging(), if PcdCpuSmmProfileEnable
is TRUE, use ConvertMemoryPageAttributes() API to map the range in
mProtectionMemRange to the attrbute recorded in the attribute field
of mProtectionMemRange, map the range outside mProtectionMemRange
as non-present. If PcdCpuSmmProfileEnable is FALSE, only need to
set the ranges not in mSmmCpuSmramRanges as NX.

Signed-off-by: Dun Tan <[email protected]>
Cc: Eric Dong <[email protected]>
Reviewed-by: Ray Ni <[email protected]>
Cc: Rahul Kumar <[email protected]>
Cc: Gerd Hoffmann <[email protected]>