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Merge pull request #93 from cr1901/up5k-leds
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Add RGB LED support to ICE40UP5K-B-EVN Target
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mithro authored Oct 29, 2018
2 parents 57fb821 + 8ed4613 commit a326dfc
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Showing 7 changed files with 42 additions and 10 deletions.
21 changes: 21 additions & 0 deletions gateware/cas.py
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@
from migen.genlib.misc import WaitTimer

from litex.soc.cores.gpio import GPIOIn, GPIOOut
from gateware.led import RGBLed

class ControlAndStatus(Module, AutoCSR):
def __init__(self, platform, clk_freq):
Expand All @@ -22,6 +23,26 @@ def __init__(self, platform, clk_freq):
except ConstraintError:
break

rgb_leds = []
while True:
try:
rgb_leds.append(platform.request("rgb_led", len(rgb_leds)))
except ConstraintError:
break
for rgb in rgb_leds:
# TODO: Common anode only for now. Support common cathode.
r_n = Signal()
g_n = Signal()
b_n = Signal()

self.comb += [
rgb.r.eq(~r_n),
rgb.g.eq(~g_n),
rgb.b.eq(~b_n),
]

user_leds.extend([r_n, g_n, b_n])

if user_leds:
leds = Signal(len(user_leds))
self.submodules.leds = GPIOOut(leds)
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6 changes: 3 additions & 3 deletions platforms/ice40_up5k_b_evn.py
Original file line number Diff line number Diff line change
Expand Up @@ -31,13 +31,13 @@

# The ICE40UP5K-B-EVN does not use the provided FT2232H chip to provide a
# UART port. One must use their own USB-to-serial cable instead to get a UART.
# We have chosen to use 37A and 36B for "tx" and "rx" respectively on Header B
# We have chosen to use 48B and 51A for "tx" and "rx" respectively on Header B
# to implement UART connections. The board comes unpopulated and will need to
# have headers soldered.
serial = [
("serial", 0,
Subsignal("tx", Pins("J2:0")),
Subsignal("rx", Pins("J2:1")),
Subsignal("tx", Pins("J2:3")),
Subsignal("rx", Pins("J2:5")),
IOStandard("LVCMOS33")
)
]
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17 changes: 14 additions & 3 deletions targets/ice40_up5k_b_evn/base.py
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,18 @@
import platforms.ice40_up5k_b_evn as up5k


# Alternate serial port, using the second 6-pin PMOD port. Follows Digilent
# PMOD Specification Type 4, so e.g. PMOD USBUART can be used.
pmod_serial = [
("serial", 0,
Subsignal("rx", Pins("PMOD:6")),
Subsignal("tx", Pins("PMOD:5")),
Subsignal("rts", Pins("PMOD:4")),
Subsignal("cts", Pins("PMOD:7")),
IOStandard("LVCMOS33"),
),
]

class _CRG(Module):
def __init__(self, platform):
clk12 = platform.request("clk12")
Expand Down Expand Up @@ -63,7 +75,7 @@ def __init__(self, platform, **kwargs):
kwargs['integrated_sram_size']=0

# FIXME: Force either lite or minimal variants of CPUs; full is too big.
platform.add_extension(up5k.serial)
platform.add_extension(pmod_serial)
platform.add_extension(up5k.spiflash)
clk_freq = int(12e6)

Expand All @@ -74,8 +86,7 @@ def __init__(self, platform, **kwargs):
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq)

# Control and Status
# TODO: Add RGB LED support to ControlAndStatus
# self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)

# SPI flash peripheral
self.submodules.spiflash = spi_flash.SpiFlashSingle(
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2 changes: 1 addition & 1 deletion third_party/litepcie

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