Showcase examples for EPFL logic synthesis libraries

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)

IDEA project source files

A circuit toolkit

This is a tutorial on standard digital design flow

A logic synthesis tool

An open-source design automation framework for Field-coupled Nanotechnologies

Toolset to capture, simulate, synthesize and verify graph models

C++ truth table library

EDA physical synthesis optimization kit

DATC RDF

Logic synthesis and ABC based optimization

C++ parsing library for simple formats used in logic synthesis and formal verification

The Verilog source code for DRUM approximate multiplier.

An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization

Awesome machine learning for logic synthesis

Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits

A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Verification""