Repurposing existing HDL tools to help writing better code

A JSON library implemented in VHDL.

Portable HyperRAM controller

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

Modelsim QEMU Unicorn integration via the FLI

Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.

A Python-based IP Core Management Infrastructure.

Utilities for Avalon Memory Map

SublimeLinter plugin for linting Verilog and SystemVerilog with Modelsim vlog

Collection of scripts for EDA tools

⚡👌 ModelSim vcom/vlog plugin for SublimeLinter. Linting for VHDL and Verilog/SystemVerilog.

In-Memory Accelerator Controller

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

A wrapper for colorizing the output of Mentor Graphics QuestaSim messages.

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directional, asynchronous and serial data transmission.It has two data lines, one to transmit (TX) and another to receive (RX) which is used to communicate th…

The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.

Latest addition to REPO : Folder with vending machine design and TB including code coverage report