Bump to latest rocket-chip

.gitmodules

@@ -129,4 +129,10 @@
 	url = https://github.com/ucb-bar/shuttle.git
 [submodule "generators/bar-fetchers"]
 	path = generators/bar-fetchers
-	url = https://github.com/ucb-bar/bar-fetchers.git
+	url = https://github.com/ucb-bar/bar-fetchers.git
+[submodule "tools/fixedpoint"]
+	path = tools/fixedpoint
+	url = https://github.com/ucb-bar/fixedpoint.git
+[submodule "generators/hardfloat"]
+	path = generators/hardfloat
+	url = https://github.com/ucb-bar/berkeley-hardfloat.git

build.sbt

@@ -95,8 +95,7 @@ lazy val chiselSettings = Seq(
 
 // -- Rocket Chip --
 
-// Rocket-chip dependencies (subsumes making RC a RootProject)
-lazy val hardfloat  = freshProject("hardfloat", rocketChipDir / "hardfloat")
+lazy val hardfloat = freshProject("hardfloat", rocketChipDir / "hardfloat/hardfloat")
   .settings(chiselSettings)
   .dependsOn(midasTargetUtils)
   .settings(commonSettings)
@@ -120,8 +119,9 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
   .settings(chiselSettings)
   .settings(
     libraryDependencies ++= Seq(
+      "com.lihaoyi" %% "mainargs" % "0.5.0",
       "org.scala-lang" % "scala-reflect" % scalaVersion.value,
-      "org.json4s" %% "json4s-jackson" % "3.6.6",
+      "org.json4s" %% "json4s-jackson" % "4.0.5",
       "org.scalatest" %% "scalatest" % "3.2.0" % "test",
       "org.scala-graph" %% "graph-core" % "1.13.5"
     )
@@ -148,7 +148,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
 lazy val chipyard = (project in file("generators/chipyard"))
   .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
     sha3, // On separate line to allow for cleaner tutorial-setup patches
-    dsptools, `rocket-dsp-utils`,
+    dsptools, rocket_dsp_utils,
     gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
     constellation, mempress, barf, shuttle)
   .settings(libraryDependencies ++= rocketLibDeps.value)
@@ -175,7 +175,7 @@ lazy val constellation = (project in file("generators/constellation"))
   .settings(commonSettings)
 
 lazy val fft_generator = (project in file("generators/fft-generator"))
-  .dependsOn(rocketchip, `rocket-dsp-utils`)
+  .dependsOn(rocketchip, rocket_dsp_utils)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
@@ -242,14 +242,20 @@ lazy val tapeout = (project in file("./tools/barstools/"))
   .settings(chiselSettings)
   .settings(commonSettings)
 
+lazy val fixedpoint = (project in file("./tools/fixedpoint/"))
+  .settings(chiselSettings)
+  .settings(commonSettings)
+
 lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
+  .dependsOn(fixedpoint)
   .settings(
     chiselSettings,
     commonSettings,
     libraryDependencies ++= Seq(
+      "edu.berkeley.cs" %% "chiseltest" % "0.6.0",
       "org.scalatest" %% "scalatest" % "3.2.+" % "test",
-      "org.typelevel" %% "spire" % "0.17.0",
-      "org.scalanlp" %% "breeze" % "1.1",
+      "org.typelevel" %% "spire" % "0.18.0",
+      "org.scalanlp" %% "breeze" % "2.1.0",
       "junit" % "junit" % "4.13" % "test",
       "org.scalacheck" %% "scalacheck" % "1.14.3" % "test",
   ))
@@ -258,7 +264,7 @@ lazy val cde = (project in file("tools/cde"))
   .settings(commonSettings)
   .settings(Compile / scalaSource := baseDirectory.value / "cde/src/chipsalliance/rocketchip")
 
-lazy val `rocket-dsp-utils` = freshProject("rocket-dsp-utils", file("./tools/rocket-dsp-utils"))
+lazy val rocket_dsp_utils = freshProject("rocket-dsp-utils", file("./tools/rocket-dsp-utils"))
   .dependsOn(rocketchip, cde, dsptools)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)

fpga/src/main/scala/arty/TestHarness.scala

@@ -25,5 +25,11 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
   def referenceClock = clock_32MHz
   def referenceReset = hReset
 
+  dut_jtag_TCK := DontCare
+  dut_jtag_TMS := DontCare
+  dut_jtag_TDI := DontCare
+  dut_jtag_TDO := DontCare
+  dut_jtag_reset := DontCare
+
   instantiateChipTops()
 }

fpga/src/main/scala/vc707/TestHarness.scala

@@ -108,6 +108,8 @@ class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModul
 
   _outer.pllReset := (resetIBUF.io.O || powerOnReset || ereset)
 
+  _outer.ledModule.foreach(_ := DontCare)
+
   // reset setup
   val hReset = Wire(Reset())
   hReset := _outer.dutClock.in.head._1.reset

generators/chipyard/src/main/scala/IOBinders.scala

@@ -225,6 +225,7 @@ class WithExtInterruptIOCells extends OverrideIOBinder({
       val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, "ext_interrupts", system.p(IOCellKey), abstractResetAsAsync = true)
       (Seq(port), cells)
     } else {
+      system.interrupts := DontCare // why do I have to drive this 0-wide wire???
       (Nil, Nil)
     }
   }
@@ -442,4 +443,13 @@ class WithDontTouchPorts extends OverrideIOBinder({
   (system: DontTouch) => system.dontTouchPorts(); (Nil, Nil)
 })
 
-
+class WithNMITiedOff extends ComposeIOBinder({
+  (system: HasTilesModuleImp) => {
+    system.nmi.flatten.foreach { nmi =>
+      nmi.rnmi := false.B
+      nmi.rnmi_interrupt_vector := 0.U
+      nmi.rnmi_exception_vector := 0.U
+    }
+    (Nil, Nil)
+  }
+})

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -45,6 +45,7 @@ class AbstractConfig extends Config(
   new chipyard.iobinders.WithNICIOPunchthrough ++
   new chipyard.iobinders.WithTraceIOPunchthrough ++
   new chipyard.iobinders.WithUARTTSIPunchthrough ++
+  new chipyard.iobinders.WithNMITiedOff ++
 
   // By default, punch out IOs to the Harness
   new chipyard.clocking.WithPassthroughClockGenerator ++

generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala

@@ -8,7 +8,7 @@ import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey, CLINTKey}
 import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI, JtagDTMKey, JtagDTMConfig}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
-import freechips.rocketchip.stage.phases.TargetDirKey
+import chipyard.stage.phases.TargetDirKey
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tile.{XLen}
 

generators/chipyard/src/main/scala/example/FlatChipTop.scala

@@ -141,5 +141,11 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
     //==========================
     require(system.uarts.size == 1)
     val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.module.uart.head, "uart_0", p(IOCellKey))
+
+
+    //==========================
+    // External interrupts (tie off)
+    //==========================
+    system.module.interrupts := DontCare
   }
 }

generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala

@@ -3,7 +3,6 @@
 package chipyard.example
 
 import chisel3._
-import chisel3.experimental.FixedPoint
 import chisel3.util._
 import dspblocks._
 import dsptools.numbers._
@@ -12,6 +11,8 @@ import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.subsystem._
+import fixedpoint._
+import fixedpoint.{fromIntToBinaryPoint, fromSIntToFixedPoint, fromUIntToFixedPoint}
 
 // FIR params
 case class GenericFIRParams(
@@ -56,7 +57,7 @@ object GenericFIRIO {
 
 // A generic FIR filter
 // DOC include start: GenericFIR chisel
-class GenericFIR[T<:Data:Ring](genIn:T, genOut:T, coeffs: Seq[T]) extends Module {
+class GenericFIR[T<:Data:Ring](genIn:T, genOut:T, coeffs: => Seq[T]) extends Module {
   val io = IO(GenericFIRIO(genIn, genOut))
 
   // Construct a vector of genericFIRDirectCells
@@ -139,7 +140,7 @@ abstract class GenericFIRBlock[D, U, EO, EI, B<:Data, T<:Data:Ring]
 (
   genIn: T,
   genOut: T,
-  coeffs: Seq[T]
+  coeffs: => Seq[T]
 )(implicit p: Parameters) extends DspBlock[D, U, EO, EI, B] {
   val streamNode = AXI4StreamIdentityNode()
   val mem = None
@@ -175,15 +176,15 @@ class TLGenericFIRBlock[T<:Data:Ring]
 (
   val genIn: T,
   val genOut: T,
-  coeffs: Seq[T]
+  coeffs: => Seq[T]
 )(implicit p: Parameters) extends
 GenericFIRBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle, T](
     genIn, genOut, coeffs
 ) with TLDspBlock
 // DOC include end: TLGenericFIRBlock chisel
 
 // DOC include start: TLGenericFIRChain chisel
-class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: Seq[T], params: GenericFIRParams)(implicit p: Parameters)
+class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: => Seq[T], params: GenericFIRParams)(implicit p: Parameters)
   extends TLChain(Seq(
     TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))(_),
     { implicit p: Parameters =>
@@ -201,7 +202,7 @@ trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
       val streamingFIR = LazyModule(new TLGenericFIRChain(
         genIn = FixedPoint(8.W, 3.BP),
         genOut = FixedPoint(8.W, 3.BP),
-        coeffs = Seq(1.F(0.BP), 2.F(0.BP), 3.F(0.BP)),
+        coeffs = Seq(1.U.asFixedPoint(0.BP), 2.U.asFixedPoint(0.BP), 3.U.asFixedPoint(0.BP)),
         params = params))
       pbus.coupleTo("streamingFIR") { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ }
       Some(streamingFIR)

generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala

@@ -7,7 +7,7 @@ import freechips.rocketchip.diplomacy.{LazyModule}
 import org.chipsalliance.cde.config.{Field, Parameters, Config}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters}
-import freechips.rocketchip.stage.phases.TargetDirKey
+import chipyard.stage.phases.TargetDirKey
 
 import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
 import chipyard.iobinders.HasIOBinders

generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala

@@ -3,8 +3,11 @@
 
 package chipyard.stage
 
-import freechips.rocketchip.stage.ConfigsAnnotation
-import firrtl.options.{HasShellOptions, ShellOption}
+import chisel3.experimental.BaseModule
+import firrtl.annotations.{Annotation, NoTargetAnnotation}
+import firrtl.options.{HasShellOptions, ShellOption, Unserializable}
+
+trait ChipyardOption extends Unserializable { this: Annotation => }
 
 /** This hijacks the existing ConfigAnnotation to accept the legacy _-delimited format  */
 private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptions {
@@ -23,3 +26,41 @@ private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptio
     )
   )
 }
+
+/** Paths to config classes */
+case class ConfigsAnnotation(configNames: Seq[String]) extends NoTargetAnnotation with ChipyardOption
+private[stage] object ConfigsAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[Seq[String]](
+      longOption = "configs",
+      toAnnotationSeq = a => Seq(ConfigsAnnotation(a)),
+      helpText = "<comma-delimited configs>",
+      shortOption = Some("C")
+    )
+  )
+}
+
+case class TopModuleAnnotation(clazz: Class[_ <: Any]) extends NoTargetAnnotation with ChipyardOption
+private[stage] object TopModuleAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[String](
+      longOption = "top-module",
+      toAnnotationSeq = a => Seq(TopModuleAnnotation(Class.forName(a).asInstanceOf[Class[_ <: BaseModule]])),
+      helpText = "<top module>",
+      shortOption = Some("T")
+    )
+  )
+}
+
+/** Optional base name for generated files' filenames */
+case class OutputBaseNameAnnotation(outputBaseName: String) extends NoTargetAnnotation with ChipyardOption
+private[stage] object OutputBaseNameAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[String](
+      longOption = "name",
+      toAnnotationSeq = a => Seq(OutputBaseNameAnnotation(a)),
+      helpText = "<base name of output files>",
+      shortOption = Some("n")
+    )
+  )
+}

generators/chipyard/src/main/scala/stage/ChipyardCli.scala

@@ -9,6 +9,9 @@ trait ChipyardCli { this: Shell =>
 
   parser.note("Chipyard Generator Options")
   Seq(
+    TopModuleAnnotation,
+    ConfigsAnnotation,
+    OutputBaseNameAnnotation,
     UnderscoreDelimitedConfigsAnnotation
   ).foreach(_.addOptions(parser))
 }

generators/chipyard/src/main/scala/stage/ChipyardOptions.scala

@@ -0,0 +1,41 @@
+// See LICENSE
+
+package chipyard.stage
+
+class ChipyardOptions private[stage] (
+                                         val topModule:         Option[Class[_ <: Any]] = None,
+                                         val configNames:       Option[Seq[String]] = None,
+                                         val outputBaseName:    Option[String] = None) {
+
+  private[stage] def copy(
+                           topModule:         Option[Class[_ <: Any]] = topModule,
+                           configNames:       Option[Seq[String]] = configNames,
+                           outputBaseName:    Option[String] = outputBaseName,
+                         ): ChipyardOptions = {
+
+    new ChipyardOptions(
+      topModule=topModule,
+      configNames=configNames,
+      outputBaseName=outputBaseName,
+    )
+  }
+
+  lazy val topPackage: Option[String] = topModule match {
+    case Some(a) => Some(a.getPackage.getName)
+    case _ => None
+  }
+
+  lazy val configClass: Option[String] = configNames match {
+    case Some(names) =>
+      val classNames = names.map{ n => n.split('.').last }
+      Some(classNames.mkString("_"))
+    case _ => None
+  }
+
+  lazy val longName: Option[String] = outputBaseName match {
+    case Some(name) => Some(name)
+    case _ =>
+      if (!topPackage.isEmpty && !configClass.isEmpty) Some(s"${topPackage.get}.${configClass.get}") else None
+  }
+}
+

generators/chipyard/src/main/scala/stage/ChipyardStage.scala

@@ -7,25 +7,35 @@ import chisel3.stage.{ChiselCli, ChiselStage}
 import firrtl.options.PhaseManager.PhaseDependency
 import firrtl.options.{Phase, PreservesAll, Shell}
 import firrtl.stage.FirrtlCli
-import freechips.rocketchip.stage.RocketChipCli
-import freechips.rocketchip.system.RocketChipStage
 
 import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain, Dependency}
 import firrtl.options.phases.DeletedWrapper
 
+final class ChipyardChiselStage extends ChiselStage {
+
+  override val targets = Seq(
+    Dependency[chisel3.stage.phases.Checks],
+    Dependency[chisel3.stage.phases.Elaborate],
+    Dependency[chisel3.stage.phases.AddImplicitOutputFile],
+    Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
+    Dependency[chisel3.stage.phases.MaybeAspectPhase],
+    Dependency[chisel3.stage.phases.Emitter],
+    Dependency[chisel3.stage.phases.Convert]
+  )
+
+}
+
 class ChipyardStage extends ChiselStage {
-  override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli
+  override val shell = new Shell("chipyard") with ChipyardCli with ChiselCli with FirrtlCli
   override val targets: Seq[PhaseDependency] = Seq(
-    Dependency[freechips.rocketchip.stage.phases.Checks],
-    Dependency[freechips.rocketchip.stage.phases.TransformAnnotations],
-    Dependency[freechips.rocketchip.stage.phases.PreElaboration],
-    // Note: Dependency[RocketChiselStage] is not listed here because it is
-    // package private, however it is named as a prereq for the passes below.
-    Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
-    Dependency[freechips.rocketchip.stage.phases.AddDefaultTests],
+    Dependency[chipyard.stage.phases.Checks],
+    Dependency[chipyard.stage.phases.TransformAnnotations],
+    Dependency[chipyard.stage.phases.PreElaboration],
+    Dependency[ChipyardChiselStage],
+    Dependency[chipyard.stage.phases.GenerateFirrtlAnnos],
     Dependency[chipyard.stage.phases.AddDefaultTests],
     Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags],
-    Dependency[freechips.rocketchip.stage.phases.GenerateArtefacts],
+    Dependency[chipyard.stage.phases.GenerateArtefacts],
   )
   override final def invalidates(a: Phase): Boolean = false
 }