Merge pull request #1636 from ucb-bar/flatchiptop_harness

Support using HarnessBinders without IOBinders

fpga/src/main/scala/arty/IOBinders.scala

@@ -18,6 +18,6 @@ class WithDebugResetPassthrough extends ComposeIOBinder({
     val io_sjtag_reset: Bool = IO(Input(Bool())).suggestName("sjtag_reset")
     sjtag.reset := io_sjtag_reset
 
-    (Seq(DebugResetPort(io_ndreset), JTAGResetPort(io_sjtag_reset)), Nil)
+    (Seq(DebugResetPort(() => io_ndreset), JTAGResetPort(() => io_sjtag_reset)), Nil)
   }
 })

fpga/src/main/scala/arty/TestHarness.scala

@@ -9,7 +9,6 @@ import org.chipsalliance.cde.config.{Parameters}
 import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
 
 import chipyard.harness.{HasHarnessInstantiators}
-import chipyard.iobinders.{HasIOBinders}
 
 class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
   // Convert harness resets from Bool to Reset type.

fpga/src/main/scala/arty100t/Harness.scala

@@ -17,7 +17,6 @@ import sifive.blocks.devices.uart._
 
 import chipyard._
 import chipyard.harness._
-import chipyard.iobinders.{HasIOBinders}
 
 class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell {
   def dp = designParameters

fpga/src/main/scala/nexysvideo/Harness.scala

@@ -16,7 +16,6 @@ import sifive.blocks.devices.uart._
 
 import chipyard._
 import chipyard.harness._
-import chipyard.iobinders.{HasIOBinders}
 
 class NexysVideoHarness(override implicit val p: Parameters) extends NexysVideoShell {
   def dp = designParameters

fpga/src/main/scala/vc707/TestHarness.scala

@@ -18,7 +18,6 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
 import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
 
 import chipyard._
-import chipyard.iobinders.{HasIOBinders}
 import chipyard.harness._
 
 class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707Shell { outer =>

fpga/src/main/scala/vcu118/TestHarness.scala

@@ -18,7 +18,6 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
 import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
 
 import chipyard._
-import chipyard.iobinders.{HasIOBinders}
 import chipyard.harness._
 
 class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays {

fpga/src/main/scala/vcu118/bringup/IOBinders.scala

@@ -13,7 +13,7 @@ import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
 
 import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort}
 
-case class TSIHostWidgetPort(val io: TSIHostWidgetIO)
+case class TSIHostWidgetPort(val getIO: () => TSIHostWidgetIO)
   extends Port[TSIHostWidgetIO]
 
 class WithTSITLIOPassthrough extends OverrideIOBinder({
@@ -25,6 +25,6 @@ class WithTSITLIOPassthrough extends OverrideIOBinder({
     require(system.tsiSerial.size == 1)
     val io_tsi_serial_pins_temp = IO(DataMirror.internal.chiselTypeClone[TSIHostWidgetIO](system.tsiSerial.head)).suggestName("tsi_serial")
     io_tsi_serial_pins_temp <> system.tsiSerial.head
-    (Seq(TLMemPort(io_tsi_tl_mem_pins_temp), TSIHostWidgetPort(io_tsi_serial_pins_temp)), Nil)
+    (Seq(TLMemPort(() => io_tsi_tl_mem_pins_temp), TSIHostWidgetPort(() => io_tsi_serial_pins_temp)), Nil)
   }
 })

generators/chipyard/src/main/scala/ChipTop.scala

@@ -8,7 +8,7 @@ import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, C
 import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
 import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}
-import freechips.rocketchip.util.{ResetCatchAndSync}
+import freechips.rocketchip.util.{DontTouch}
 import chipyard.iobinders._
 
 import barstools.iocell.chisel._
@@ -31,5 +31,5 @@ class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope
   // of ChipTop (ex: ClockGroup) do not receive clock or reset.
   // However. anonymous children of ChipTop should not need an implicit Clock or Reset
   // anyways, they probably need to be explicitly clocked.
-  lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) {  }
+  lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) with DontTouch {  }
 }

generators/chipyard/src/main/scala/clocking/ClockBinders.scala

@@ -75,11 +75,11 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
         o.reset := reset_wire
       }
 
-      (Seq(ClockPort(clock_io, 100), ResetPort(reset_io)), clockIOCell ++ resetIOCell)
+      (Seq(ClockPort(() => clock_io, 100), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell)
     }
   }
 })
-
+ 
 // This passes all clocks through to the TestHarness
 class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
   (system: HasChipyardPRCI) => {
@@ -113,9 +113,9 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
         val clock_io = IO(Input(Clock())).suggestName(s"clock_${m.name.get}")
         b.clock := clock_io
         b.reset := reset_io
-        ClockPort(clock_io, freq)
+        ClockPort(() => clock_io, freq)
       }.toSeq
-      ((clock_ios :+ ResetPort(reset_io)), Nil)
+      ((clock_ios :+ ResetPort(() => reset_io)), Nil)
     }
   }
 })

generators/chipyard/src/main/scala/config/ChipConfigs.scala

@@ -43,6 +43,10 @@ class ChipLikeRocketConfig extends Config(
 
   new chipyard.config.AbstractConfig)
 
+class FlatChipTopChipLikeRocketConfig extends Config(
+  new chipyard.example.WithFlatChipTop ++
+  new chipyard.ChipLikeRocketConfig)
+
 // A simple config demonstrating a "bringup prototype" to bringup the ChipLikeRocketconfig
 class ChipBringupHostConfig extends Config(
   //=============================

generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala

@@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
 // DOC include start: FFTRocketConfig
 class FFTRocketConfig extends Config(
-  new chipyard.iobinders.WithDontTouchIOBinders(false) ++              // TODO: hack around dontTouch not working in SFC
+  new chipyard.harness.WithDontTouchChipTopPorts(false) ++              // TODO: hack around dontTouch not working in SFC
   new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
@@ -59,7 +59,7 @@ class LargeNVDLARocketConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class ManyMMIOAcceleratorRocketConfig extends Config(
-  new chipyard.iobinders.WithDontTouchIOBinders(false) ++   // TODO: hack around dontTouch not working in SFC
+  new chipyard.harness.WithDontTouchChipTopPorts(false) ++   // TODO: hack around dontTouch not working in SFC
   new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
   new chipyard.example.WithStreamingPassthrough ++          // use top with tilelink-controlled streaming passthrough
   new chipyard.example.WithStreamingFIR ++                  // use top with tilelink-controlled streaming FIR

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -12,7 +12,7 @@ class RocketConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class TinyRocketConfig extends Config(
-  new chipyard.iobinders.WithDontTouchIOBinders(false) ++         // TODO FIX: Don't dontTouch the ports
+  new chipyard.harness.WithDontTouchChipTopPorts(false) ++         // TODO FIX: Don't dontTouch the ports
   new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology
   new freechips.rocketchip.subsystem.WithNBanks(0) ++             // remove L2$
   new freechips.rocketchip.subsystem.WithNoMemPort ++             // remove backing memory
@@ -97,6 +97,7 @@ class MulticlockRocketConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class CustomIOChipTopRocketConfig extends Config(
+  new chipyard.example.WithBrokenOutUARTIO ++
   new chipyard.example.WithCustomChipTop ++
   new chipyard.example.WithCustomIOCells ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core

generators/chipyard/src/main/scala/config/TutorialConfigs.scala

@@ -77,7 +77,7 @@ class TutorialSha3BlackBoxConfig extends Config(
 
 // Tutorial Phase 5: Map a multicore heterogeneous SoC with multiple cores and memory-mapped accelerators
 class TutorialNoCConfig extends Config(
-  new chipyard.iobinders.WithDontTouchIOBinders(false) ++
+  new chipyard.harness.WithDontTouchChipTopPorts(false) ++
   // Try changing the dimensions of the Mesh topology
   new constellation.soc.WithGlobalNoC(constellation.soc.GlobalNoCParams(
     NoCParams(

generators/chipyard/src/main/scala/example/CustomChipTop.scala

@@ -5,9 +5,11 @@ import chipyard.iobinders._
 
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.diplomacy.{InModuleBody}
+import freechips.rocketchip.subsystem.{PBUS, HasTileLinkLocations}
 import barstools.iocell.chisel._
 import chipyard._
 import chipyard.harness.{BuildTop}
+import sifive.blocks.devices.uart._
 
 // A "custom" IOCell with additional I/O
 // The IO don't do anything here in this example
@@ -63,3 +65,21 @@ class WithCustomIOCells extends Config((site, here, up) => {
 class WithCustomChipTop extends Config((site, here, up) => {
   case BuildTop => (p: Parameters) => new CustomChipTop()(p)
 })
+
+class WithBrokenOutUARTIO extends OverrideIOBinder({
+  (system: HasPeripheryUARTModuleImp) => {
+    val uart_txd = IO(Output(Bool()))
+    val uart_rxd = IO(Input(Bool()))
+    system.uart(0).rxd := uart_rxd
+    uart_txd := system.uart(0).txd
+    val where = PBUS // TODO fix
+    val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
+    val freqMHz = bus.dtsFrequency.get / 1000000
+    (Seq(UARTPort(() => {
+      val uart_wire = Wire(new UARTPortIO(system.uart(0).c))
+      uart_wire.txd := uart_txd
+      uart_rxd := uart_wire.rxd
+      uart_wire
+    }, 0, freqMHz.toInt)), Nil)
+  }
+})

generators/chipyard/src/main/scala/example/FlatChipTop.scala

@@ -2,22 +2,28 @@ package chipyard.example
 
 
 import chisel3._
-import org.chipsalliance.cde.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Config, Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.util._
+import freechips.rocketchip.subsystem.{PBUS, HasTileLinkLocations}
 import freechips.rocketchip.devices.debug.{ExportDebug, JtagDTMKey, Debug}
 import freechips.rocketchip.tilelink.{TLBuffer, TLFragmenter}
 import chipyard.{BuildSystem, DigitalTop}
+import chipyard.harness.{BuildTop}
 import chipyard.clocking._
-import chipyard.iobinders.{IOCellKey, JTAGChipIO}
+import chipyard.iobinders._
 import barstools.iocell.chisel._
+import testchipip.{SerialTLKey}
 
+class WithFlatChipTop extends Config((site, here, up) => {
+  case BuildTop => (p: Parameters) => new FlatChipTop()(p)
+})
 
 // This "FlatChipTop" uses no IOBinders, so all the IO have
 // to be explicitly constructed.
 // This only supports the base "DigitalTop"
-class FlatChipTop(implicit p: Parameters) extends LazyModule {
+class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPorts {
   override lazy val desiredName = "ChipTop"
   val system = LazyModule(p(BuildSystem)(p)).suggestName("system").asInstanceOf[DigitalTop]
 
@@ -56,6 +62,8 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
   debugClockSinkNode := system.locateTLBusWrapper(p(ExportDebug).slaveWhere).fixedClockNode
   def debugClockBundle = debugClockSinkNode.in.head._1
 
+  var ports: Seq[Port[_]] = Nil
+
   override lazy val module = new FlatChipTopImpl
   class FlatChipTopImpl extends LazyRawModuleImp(this) {
     //=========================
@@ -78,6 +86,9 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
       o.reset := reset_wire
     }
 
+    ports = ports :+ ClockPort(() => clock_pad, 100.0)
+    ports = ports :+ ResetPort(() => reset_pad)
+
     // For a real chip you should replace this ClockSourceAtFreqFromPlusArg
     // with a blackbox of whatever PLL is being integrated
     val fake_pll = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz"))
@@ -93,11 +104,13 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
     // Custom Boot
     //=========================
     val (custom_boot_pad, customBootIOCell) = IOCell.generateIOFromSignal(system.custom_boot_pin.get.getWrappedValue, "custom_boot", p(IOCellKey))
+    ports = ports :+ CustomBootPort(() => custom_boot_pad)
 
     //=========================
     // Serialized TileLink
     //=========================
     val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tl.get.getWrappedValue, "serial_tl", p(IOCellKey))
+    ports = ports :+ SerialTLPort(() => serial_tl_pad, p(SerialTLKey).get, system.serdesser.get, 0)
 
     //=========================
     // JTAG/Debug
@@ -136,12 +149,17 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
       IOCell.generateIOFromSignal(jtag_wire, "jtag", p(IOCellKey), abstractResetAsAsync = true)
     }.get
 
+    ports = ports :+ JTAGPort(() => jtag_pad)
+
     //==========================
     // UART
     //==========================
     require(system.uarts.size == 1)
     val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.module.uart.head, "uart_0", p(IOCellKey))
-
+    val where = PBUS // TODO fix
+    val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
+    val freqMHz = bus.dtsFrequency.get / 1000000
+    ports = ports :+ UARTPort(() => uart_pad, 0, freqMHz.toInt)
 
     //==========================
     // External interrupts (tie off)

generators/chipyard/src/main/scala/harness/HarnessClocks.scala

@@ -10,7 +10,6 @@ import freechips.rocketchip.util.{ResetCatchAndSync}
 import freechips.rocketchip.prci._
 
 import chipyard.harness.{ApplyHarnessBinders, HarnessBinders, HarnessClockInstantiatorKey}
-import chipyard.iobinders.HasIOBinders
 import chipyard.clocking.{SimplePllConfiguration, ClockDividerN}
 
 

generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala

@@ -5,12 +5,12 @@ import chisel3._
 import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
 import freechips.rocketchip.diplomacy.{LazyModule}
 import org.chipsalliance.cde.config.{Field, Parameters, Config}
-import freechips.rocketchip.util.{ResetCatchAndSync}
+import freechips.rocketchip.util.{ResetCatchAndSync, DontTouch}
 import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters}
 import chipyard.stage.phases.TargetDirKey
 
 import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
-import chipyard.iobinders.HasIOBinders
+import chipyard.iobinders.HasChipyardPorts
 import chipyard.clocking.{SimplePllConfiguration, ClockDividerN}
 import chipyard.{ChipTop}
 
@@ -24,6 +24,7 @@ case object BuildTop extends Field[Parameters => LazyModule]((p: Parameters) =>
 case object HarnessClockInstantiatorKey extends Field[() => HarnessClockInstantiator]()
 case object HarnessBinderClockFrequencyKey extends Field[Double](100.0) // MHz
 case object MultiChipIdx extends Field[Int](0)
+case object DontTouchChipTopPorts extends Field[Boolean](true)
 
 class WithMultiChip(id: Int, p: Parameters) extends Config((site, here, up) => {
   case MultiChipParameters(`id`) => p
@@ -39,6 +40,10 @@ class WithHarnessBinderClockFreqMHz(freqMHz: Double) extends Config((site, here,
   case HarnessBinderClockFrequencyKey => freqMHz
 })
 
+class WithDontTouchChipTopPorts(b: Boolean = true) extends Config((site, here, up) => {
+  case DontTouchChipTopPorts => b
+})
+
 // A TestHarness mixing this in will
 // - use the HarnessClockInstantiator clock provide
 trait HasHarnessInstantiators {
@@ -83,12 +88,20 @@ trait HasHarnessInstantiators {
 
     withClockAndReset (harnessBinderClock, harnessBinderReset) {
       lazyDuts.zipWithIndex.foreach {
-        case (d: HasIOBinders, i: Int) => ApplyHarnessBinders(this, d.portMap.values.flatten.toSeq)(chipParameters(i))
+        case (d: HasChipyardPorts, i: Int) => {
+          ApplyHarnessBinders(this, d.ports)(chipParameters(i))
+        }
         case _ =>
       }
       ApplyMultiHarnessBinders(this, lazyDuts)
     }
 
+    if (p(DontTouchChipTopPorts)) {
+      duts.map(_ match {
+        case d: DontTouch => d.dontTouchPorts()
+      })
+    }
+
     val harnessBinderClk = harnessClockInstantiator.requestClockMHz("harnessbinder_clock", getHarnessBinderClockFreqMHz)
     println(s"Harness binder clock is $harnessBinderClockFreq")
     harnessBinderClock := harnessBinderClk

generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala

@@ -13,7 +13,7 @@ import freechips.rocketchip.util._
 import testchipip._
 
 import chipyard._
-import chipyard.iobinders.{GetSystemParameters, JTAGChipIO, HasIOBinders, Port, SerialTLPort}
+import chipyard.iobinders.{GetSystemParameters, JTAGChipIO, HasChipyardPorts, Port, SerialTLPort}
 
 import scala.reflect.{ClassTag}
 
@@ -23,8 +23,8 @@ object ApplyMultiHarnessBinders {
   def apply(th: HasHarnessInstantiators, chips: Seq[LazyModule])(implicit p: Parameters): Unit = {
     Seq.tabulate(chips.size, chips.size) { case (i, j) => if (i != j) {
       (chips(i), chips(j)) match {
-        case (l0: HasIOBinders, l1: HasIOBinders) => p(MultiHarnessBinders(i, j)).foreach { f =>
-          f(l0.portMap.values.flatten.toSeq, l1.portMap.values.flatten.toSeq)
+        case (l0: HasChipyardPorts, l1: HasChipyardPorts) => p(MultiHarnessBinders(i, j)).foreach { f =>
+          f(l0.ports, l1.ports)
         }
       }
     }}

generators/chipyard/src/main/scala/harness/TestHarness.scala

@@ -9,7 +9,6 @@ import freechips.rocketchip.util.{ResetCatchAndSync}
 import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters}
 
 import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
-import chipyard.iobinders.HasIOBinders
 import chipyard.clocking.{SimplePllConfiguration, ClockDividerN}
 import chipyard.{ChipTop}