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I want to generate my own custom SOC to burn a bitstream file to a supported development board (i.e. not limited to the off-the-shelf configuration provided by the config.scala file in the FPGA/src/main/scala/board folder) What configuration should I add?
Motivating Example
For example, I want to generate a CVA6+AXI based SOC in Nexysvideo.However,there is no related configuration about CVA6 in the
config.scala under FPGA/src/main/scala/board folder
The text was updated successfully, but these errors were encountered:
You'll have to construct the configuration yourself, matching what was done for the example configurations for that board
by the way,i want to combine CVA6 +ARA in chipyard ,I don't know how to start at the moment, should I use chisel to exemplify cva6 blackbox.scala and ara blackbox.scala?
Ah, I did not realize you wanted to do CVA6+Ara. That is not supported in
CY at the moment, the CVA6 and Ara blocks are independent IPs that are not
combinable in the chisel wrappers.
The approach would be to create a new Chisel tile wrapper - "CVA6AraTile"
that wraps a combined CVA6+Ara system.
Background Work
Feature Description
I want to generate my own custom SOC to burn a bitstream file to a supported development board (i.e. not limited to the off-the-shelf configuration provided by the config.scala file in the FPGA/src/main/scala/board folder) What configuration should I add?
Motivating Example
For example, I want to generate a CVA6+AXI based SOC in Nexysvideo.However,there is no related configuration about CVA6 in the
config.scala under FPGA/src/main/scala/board folder
The text was updated successfully, but these errors were encountered: