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I rebuild the emulator with some revisions. I rebuild the project again without typing "make clean" before.
It takes about first time.
I use make -d to observe the hanging point that costs lots of time at rebuild.
hanging point:
The prerequisites of 'default' are being made.
Live child 0xaddc20 (VTestHarness.o) PID 31961
It seems it recompile to generate out VTestHarness.o(I am not sure) .
I cannot figure out why? Could anyone tells me the reasons?
The text was updated successfully, but these errors were encountered:
I would also be interested if someone knows the reason! I've noticed the same phenomenon, and it would be great to be able to make minor changes to a configuration without rebuilding the entire thing from scratch!
This is an unfortunate limitation of how verilator works. When you change the verilog in any way, verilator will create an entirely new set of C++ files, so they will all get rebuilt.
* Correct multi-ported memory compilation
It was incorrectly splitting multiple times before. Fixed the issue and
added regression tests for this issue.
* Add 1 read 1 write test
I rebuild the emulator with some revisions. I rebuild the project again without typing "make clean" before.
It takes about first time.
I use make -d to observe the hanging point that costs lots of time at rebuild.
hanging point:
It seems it recompile to generate out VTestHarness.o(I am not sure) .
I cannot figure out why? Could anyone tells me the reasons?
The text was updated successfully, but these errors were encountered: