Use fat jar's to remove SBT invocations

[abejgonzalez]

Since the SBT thin client is brittle (can sometimes not read in SBT_OPTS, and other issues in the past), this PR will instead remove the thin client feature and instead build a fat jar to avoid SBT invocations. This also helps future work in distributing Chisel elaboration to multiple hosts (i.e. just needing to copy the fat jar to generate Verilog in parallel on different machines).

This repurposing a lot of the work that was done in: #872 and firesim/firesim#651 with inspiration from firesim/firesim#1390

• Some submodules had to be updated. Specifically, if a SBT project's resource path clashed with another project's resource path, it would fail. Ex. - PrjA has a file in src/main/rsrc/Makefile and PrjB also has a file in the same path it would error.
• This has some small build.sbt cleanup to avoid other misc. sbt assembly errors. The deps removed are not needed.

Related PRs / Issues:

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other

Contributor Checklist:

• Did you set main as the base branch?
• Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
• Did you state the type-of-change/impact?
• Did you delete any extraneous prints/debugging code?
• Did you mark the PR with a changelog: label?
• (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
• (If applicable) Did you add documentation for the feature?
• (If applicable) Did you add a test demonstrating the PR?

• (If applicable) Did you mark the PR as Please Backport?

[abejgonzalez]

This is cleanup (these deps aren't needed)

[jerryz123]

Can you check this ?

• run make verilog
• touch/edit a random source file
• run time make verilog

[abejgonzalez]

In a clean repo, after running the setup.

• run time make verilog -> 1m37s
• touch/edit a random source file -> touched DigitalTop.scala
• run time make verilog -> incremental compile worked - 40s

[abejgonzalez]

Closing since #1362 solves the initial issue I was trying to solve. I'll add this after the release if time permits.

[abejgonzalez]

This PR can be independently merged in separate from FireSim (see https://github.com/firesim/firesim/actions/runs/5010945519)

[jerryz123]

Looks fine to merge once the CI passes.