Improvements to chipyard clocking

[jerryz123]

Localizes all the clock devices to prci_ctrl_domain, and adds a xbar for all the clock control devices.
This should improve physical design of clock/reset devices, since it all is under a single module hierarchically with fewer IO

Fixes TLClockDivider behavior.
Previously, if the divisor register somehow misses the reset pulse, it would set the DividerOrPass to a bad state that could initialize the system to a very slow clock. This would never happen in a physical implementation.

However, in RTL simulations where the power-reset sequence is not totally simulated, only a negedge reset might be evaluated with no posedge reset. Since the AsyncResetRegs are sensitive to posedge reset or posedge clock, and the asyncReset may deassert before a clock arrives at the TLBus, that register might never be reset in simulation.

This fix overall makes the system more robust, it forces the DivideOrPass to output the undivided clock until the TL bus clock is alive, and the TL bus reset is deasserted, regardless of the value of the divisor register. The divisor register is now reset by the TL bus reset as well, which guarantees that it would be reset properly under any RTL simulation, as the TL bus reset should be deasserted after the TL bus clock is alive.

Fixes divisor synchronization
The divisor register is clocked to the TL bus clock, but it needs to be synchronized to the clock it is dividing (which may not be the same). The testchipip bump fixes this.

Explicitly use RawModules
Blocks which produce clocks/reset/sync-issues should not use implicit clock/reset, it is too confusing. The ClockDivideOrPass is now a RawModule.

Related PRs / Issues:

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other

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