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Fix Arty100T verilog build #1608

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Sep 27, 2023
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3 changes: 2 additions & 1 deletion .github/scripts/defaults.sh
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@ grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipya
grouping["group-constellation"]="chipyard-constellation"
grouping["group-tracegen"]="tracegen tracegen-boom"
grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar"
grouping["group-fpga"]="arty vcu118 vc707"
grouping["group-fpga"]="arty vcu118 vc707 arty100t"

# key value store to get the build strings
declare -A mapping
Expand Down Expand Up @@ -81,3 +81,4 @@ mapping["rocketchip-tlxbar"]="SUB_PROJECT=rocketchip CONFIG=TLXbarUnitTestConfig
mapping["arty"]="SUB_PROJECT=arty verilog"
mapping["vcu118"]="SUB_PROJECT=vcu118 verilog"
mapping["vc707"]="SUB_PROJECT=vc707 verilog"
mapping["arty100t"]="SUB_PROJECT=arty100t verilog"
2 changes: 1 addition & 1 deletion fpga/fpga-shells
1 change: 1 addition & 0 deletions fpga/src/main/scala/arty100t/Harness.scala
Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,7 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
override lazy val module = new HarnessLikeImpl

class HarnessLikeImpl extends Impl with HasHarnessInstantiators {
all_leds.foreach(_ := DontCare)
clockOverlay.overlayOutput.node.out(0)._1.reset := ~resetPin

val clk_100mhz = clockOverlay.overlayOutput.node.out.head._1.clock
Expand Down