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Remove legacy SFC flags #1859

Merged
merged 10 commits into from
Apr 30, 2024
Merged

Remove legacy SFC flags #1859

merged 10 commits into from
Apr 30, 2024

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jerryz123
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Fixed types are never generated now. Custom SFC passes/flags are not known to be used. Preps the way for chisel6

Related PRs / Issues:

Type of change:

  • Bug fix
  • New feature
  • Other enhancement

Impact:

  • RTL change
  • Software change (RISC-V software)
  • Build system change
  • Other

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  • Did you set main as the base branch?
  • Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
  • Did you state the type-of-change/impact?
  • Did you delete any extraneous prints/debugging code?
  • Did you mark the PR with a changelog: label?
  • (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
  • (If applicable) Did you add documentation for the feature?
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  • (If applicable) Did you mark the PR as Please Backport?

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@abejgonzalez abejgonzalez left a comment

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I would just fork the flow into 2:

  1. Normal - Chisel Generator -> MFC -> Verilog
  2. Experimental - Chisel Generator -> SFC -> MFC (or potentially skip this) -> Verilog

The "experimental" side of it would be untested and up to power users to bugfix (IMO this pushes users to write MFC passes which can now be out-of-tree injected)

@jerryz123
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I would just fork the flow into 2:

  1. Normal - Chisel Generator -> MFC -> Verilog
  2. Experimental - Chisel Generator -> SFC -> MFC (or potentially skip this) -> Verilog

The "experimental" side of it would be untested and up to power users to bugfix (IMO this pushes users to write MFC passes which can now be out-of-tree injected)

Do we have any evidence anyone wants 2? This will fundamentally not work with chisel6, as the chisel6 emitted CHIRRTL is not compatible with SFC.

Assuming this gets in, my initial chisel6 PRs will allow the users to choose whether to compile with chisel6 or chisel3.
RTL sims can be the first to move over completely to chisel6. Then the VLSI and FPGA flows. And then firesim (I think I see a way to make this work with minimal intrusiveness).
Only once all flows are in chisel6, will we drop chisel3 support entirely.

@jerryz123
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Also, see in #1860 that this enables removing all of GenerateModelStageMain, which I see as a huge benefit, and after that is done, the makefile flow is drastically simplified.

@abejgonzalez
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I think some people wanted an SFC option (instead of having to write MFC passes) but I don't think anyone was using the SFC passes currently (only people who've used them in the past). I'm personally pro-removing-SFC (but I haven't used the pass injection in years) but I remember having a conversation w/ folks on keeping/removing it hence the recommendation.

@jerryz123
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A clean transition to chisel6 is not possible without removing this seldom-used feature.

Once the RTL-sim flow is in Chisel6, I'll submit another PR allowing a chisel6 frontend to use SFC firrtl passes, for firesim.

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@abejgonzalez abejgonzalez left a comment

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LGTM

@jerryz123 jerryz123 merged commit 25589d6 into main Apr 30, 2024
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2 participants