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Fix classpath_cache bug #1880

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merged 4 commits into from
May 16, 2024
Merged

Fix classpath_cache bug #1880

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c60d047
remove redundant CLASSPATH_TARGETS (this is always the same as CLASSP…
jerryz123 May 16, 2024
9737d62
Add comments on what CHIPYARD_CLASSPATH and TAPEOUT_CLASSPATH contain
jerryz123 May 16, 2024
0c3ede1
Rename CHIPYARD_CLASSPATH to GENERATOR_CLASSPATH
jerryz123 May 16, 2024
3cf3d81
Rename fpga_platforms to chipyard_fpga
jerryz123 May 16, 2024
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2 changes: 1 addition & 1 deletion build.sbt
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Expand Up @@ -324,6 +324,6 @@ lazy val fpga_shells = (project in file("./fpga/fpga-shells"))
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)

lazy val fpga_platforms = (project in file("./fpga"))
lazy val chipyard_fpga = (project in file("./fpga"))
.dependsOn(chipyard, fpga_shells)
.settings(commonSettings)
14 changes: 7 additions & 7 deletions common.mk
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Expand Up @@ -119,23 +119,23 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
#########################################################################################
# compile scala jars
#########################################################################################
$(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES)
$(GENERATOR_CLASSPATH) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES)
$(CHECK_SUBMODULES_COMMAND)
mkdir -p $(dir $@)
$(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH))
$(call run_sbt_assembly,$(SBT_PROJECT),$(GENERATOR_CLASSPATH))

# order only dependency between sbt runs needed to avoid concurrent sbt runs
$(TAPEOUT_CLASSPATH_TARGETS) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH_TARGETS)
$(TAPEOUT_CLASSPATH) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(GENERATOR_CLASSPATH)
mkdir -p $(dir $@)
$(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH))

#########################################################################################
# verilog generation pipeline
#########################################################################################
# AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile
$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(CHIPYARD_CLASSPATH_TARGETS) $(EXTRA_GENERATOR_REQS)
$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(GENERATOR_CLASSPATH) $(EXTRA_GENERATOR_REQS)
mkdir -p $(build_dir)
(set -o pipefail && $(call run_jar_scala_main,$(CHIPYARD_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\
(set -o pipefail && $(call run_jar_scala_main,$(GENERATOR_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\
--target-dir $(build_dir) \
--name $(long_name) \
--top-module $(MODEL_PACKAGE).$(MODEL) \
Expand Down Expand Up @@ -242,12 +242,12 @@ $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JS

# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
TOP_MACROCOMPILER_MODE ?= --mode synflops
$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(TOP_SMEMS_CONF)
$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH) $(TOP_SMEMS_CONF)
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE))
touch $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR)

MODEL_MACROCOMPILER_MODE = --mode synflops
$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_SMEMS_CONF)
$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH) $(MODEL_SMEMS_CONF)
$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE))
touch $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR)

Expand Down
2 changes: 1 addition & 1 deletion docs/Prototyping/General.rst
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Expand Up @@ -30,7 +30,7 @@ For example:

# converts to

make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 FPGA_BRAND=... bitstream
make SBT_PROJECT=chipyard_fpga MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 FPGA_BRAND=... bitstream

Some ``SUB_PROJECT`` defaults are already defined for use, including ``vcu118`` and ``arty``.
These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more for the Chipyard make system.
Expand Down
10 changes: 5 additions & 5 deletions fpga/Makefile
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Expand Up @@ -17,7 +17,7 @@ sim_name := none
SUB_PROJECT ?= vcu118

ifeq ($(SUB_PROJECT),vc707)
SBT_PROJECT ?= fpga_platforms
SBT_PROJECT ?= chipyard_fpga
MODEL ?= VC707FPGATestHarness
VLOG_MODEL ?= VC707FPGATestHarness
MODEL_PACKAGE ?= chipyard.fpga.vc707
Expand All @@ -31,7 +31,7 @@ ifeq ($(SUB_PROJECT),vc707)
endif

ifeq ($(SUB_PROJECT),vcu118)
SBT_PROJECT ?= fpga_platforms
SBT_PROJECT ?= chipyard_fpga
MODEL ?= VCU118FPGATestHarness
VLOG_MODEL ?= VCU118FPGATestHarness
MODEL_PACKAGE ?= chipyard.fpga.vcu118
Expand All @@ -45,7 +45,7 @@ ifeq ($(SUB_PROJECT),vcu118)
endif

ifeq ($(SUB_PROJECT),nexysvideo)
SBT_PROJECT ?= fpga_platforms
SBT_PROJECT ?= chipyard_fpga
MODEL ?= NexysVideoHarness
VLOG_MODEL ?= NexysVideoHarness
MODEL_PACKAGE ?= chipyard.fpga.nexysvideo
Expand All @@ -60,7 +60,7 @@ endif

ifeq ($(SUB_PROJECT),arty35t)
# TODO: Fix with Arty
SBT_PROJECT ?= fpga_platforms
SBT_PROJECT ?= chipyard_fpga
MODEL ?= Arty35THarness
VLOG_MODEL ?= Arty35THarness
MODEL_PACKAGE ?= chipyard.fpga.arty
Expand All @@ -74,7 +74,7 @@ ifeq ($(SUB_PROJECT),arty35t)
endif
ifeq ($(SUB_PROJECT),arty100t)
# TODO: Fix with Arty
SBT_PROJECT ?= fpga_platforms
SBT_PROJECT ?= chipyard_fpga
MODEL ?= Arty100THarness
VLOG_MODEL ?= Arty100THarness
MODEL_PACKAGE ?= chipyard.fpga.arty100t
Expand Down
7 changes: 3 additions & 4 deletions variables.mk
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Expand Up @@ -160,11 +160,10 @@ endif

# classpaths
CLASSPATH_CACHE ?= $(base_dir)/.classpath_cache
CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/chipyard.jar
# The generator classpath must contain the Generator main
GENERATOR_CLASSPATH ?= $(CLASSPATH_CACHE)/$(SBT_PROJECT).jar
# The tapeout classpath must contain MacroCompiler
TAPEOUT_CLASSPATH ?= $(CLASSPATH_CACHE)/tapeout.jar
# if *_CLASSPATH is a true java classpath, it can be colon-delimited list of paths (on *nix)
CHIPYARD_CLASSPATH_TARGETS ?= $(subst :, ,$(CHIPYARD_CLASSPATH))
TAPEOUT_CLASSPATH_TARGETS ?= $(subst :, ,$(TAPEOUT_CLASSPATH))

# chisel generated outputs
FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
Expand Down
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