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Fix clock name and macro paths for Sky130 VLSI flow #1882

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merged 1 commit into from
May 20, 2024
Merged

Fix clock name and macro paths for Sky130 VLSI flow #1882

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2 changes: 1 addition & 1 deletion vlsi/example-asap7.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ vlsi.inputs.power_spec_type: "cpf"

# Specify clock signals
vlsi.inputs.clocks: [
{name: "clock_uncore_clock", period: "1ns", uncertainty: "0.1ns"}
{name: "clock_uncore", period: "1ns", uncertainty: "0.1ns"}
]

# Generate Make include to aid in flow
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2 changes: 1 addition & 1 deletion vlsi/example-design.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ vlsi.inputs.power_spec_type: "cpf"

# Specify clock signals
vlsi.inputs.clocks: [
{name: "clock_uncore_clock", period: "2ns", uncertainty: "0.1ns"}
{name: "clock_uncore", period: "2ns", uncertainty: "0.1ns"}
]

# Specify pin properties
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2 changes: 1 addition & 1 deletion vlsi/example-designs/sky130-commercial.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@

# Specify clock signals
vlsi.inputs.clocks: [
{name: "clock_uncore_clock", period: "30ns", uncertainty: "2ns"}
{name: "clock_uncore", period: "30ns", uncertainty: "2ns"}
]

# Placement Constraints
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5 changes: 3 additions & 2 deletions vlsi/example-designs/sky130-openroad-rockettile.yml
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
# Override configurations in ../example-sky130.yml and example-designs

# Specify clock signals
# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock"
# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore"
vlsi.inputs.clocks: [
{name: "clock", period: "30ns", uncertainty: "3ns"}
]
Expand All @@ -22,7 +22,7 @@ vlsi.inputs.placement_constraints:
bottom: 10

# Place SRAM memory instances
# data cache
# data cache
- path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
type: hardmacro
x: 50
Expand All @@ -47,3 +47,4 @@ vlsi.inputs.placement_constraints:
x: 50
y: 2100
orientation: r90

23 changes: 7 additions & 16 deletions vlsi/example-designs/sky130-openroad.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
# Specify clock signals
# Relax the clock period for OpenROAD to meet timing
vlsi.inputs.clocks: [
{name: "clock_uncore_clock", period: "50ns", uncertainty: "2ns"}
{name: "clock_uncore", period: "50ns", uncertainty: "2ns"}
]

# Flow parameters that yield a routable design with reasonable timing
Expand Down Expand Up @@ -54,36 +54,27 @@ vlsi.inputs.placement_constraints:
bottom: 10

# Place SRAM memory instances
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
# data cache
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 50
orientation: r90
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
type: hardmacro
x: 50
y: 450
orientation: r90
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 850
orientation: r90
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 1250
y: 800
orientation: r90

# tag array
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 1600
orientation: r90

# instruction cache
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 2100
Expand Down
2 changes: 1 addition & 1 deletion vlsi/example-designs/sky130-rocket.yml
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
# Override configurations in ../example-sky130.yml and example-designs

# Specify clock signals
# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock"
# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore"
vlsi.inputs.clocks: [
{name: "clock", period: "5ns", uncertainty: "1ns"}
]
Expand Down
12 changes: 6 additions & 6 deletions vlsi/example-sky130.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@ vlsi.inputs.power_spec_type: "cpf"

# Specify clock signals
vlsi.inputs.clocks: [
{name: "clock_uncore_clock", period: "20ns", uncertainty: "1ns"}
{name: "clock_uncore", period: "20ns", uncertainty: "1ns"}
]

# Generate Make include to aid in flow
Expand All @@ -42,27 +42,27 @@ vlsi.inputs.placement_constraints:
bottom: 10

# Place SRAM memory instances
# data cache
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
# data cache
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 50
orientation: r90
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
type: hardmacro
x: 50
y: 800
orientation: r90

# tag array
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 1600
orientation: r90

# instruction cache
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 2100
Expand Down
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