Bump toolchains/riscv-tools/riscv-isa-sim from 1b80449 to 3c5b1bb
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Bumps [toolchains/riscv-tools/riscv-isa-sim](https://github.com/riscv-software-src/riscv-isa-sim) from `1b80449` to `3c5b1bb`. - [Release notes](https://github.com/riscv-software-src/riscv-isa-sim/releases) - [Commits](riscv-software-src/riscv-isa-sim@1b80449...3c5b1bb) --- updated-dependencies: - dependency-name: toolchains/riscv-tools/riscv-isa-sim dependency-type: direct:production ... Signed-off-by: dependabot[bot] <[email protected]>
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Bumps toolchains/riscv-tools/riscv-isa-sim from
1b80449to3c5b1bb.Commits
3c5b1bbMerge pull request #1779 from rtwfroody/trigger_timing3f556d6Merge pull request #1791 from YenHaoChen/pr-pm84a212epointer masking: Always apply sstatus.MXR regardless of effective V272c149Merge pull request #1789 from YenHaoChen/pr-pm61d277cpointer masking: Consider effective v bit instead of current v bit5029aa7Merge pull request #1787 from riscv-software-src/fix-cfg-priv60f02ddMerge pull request #1786 from YenHaoChen/pr-mcontroleb07f10Use cmdline --priv flag when parsing proc configurations from DTB1510a6etriggers: Let mcontrol.match be default (0/equal) if maskmax is 0d13dc0btriggers: mcontrol: refactor: Add mcontrol_t::maskmaxDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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