Add example accelerator using HLS #2056
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| the Great Common Denominator (GCD) of two integers. This tutorial | ||
| builds on the sections :ref:`mmio-accelerators` and | ||
| :ref:`incorporating-verilog-blocks`. The code for this example can | ||
| be found in ``/generators/hls-example`` |
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I would use gh-file-ref to have it auto-generate a link:
| Adding an HLS project | ||
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| In this tutorial, we use Vitis HLS, version 2023.2. |
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The CI is using an older version of the tool FYI.
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Also maybe I would point to some docs/link to Vitis HLS. Isn't there restrictions on where this can be used (and if so, should we mention something about that here)?
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I looked closer on the product site and the documentation but I couldn't find any restrictions on where Vitis HLS can be used. Possibly it's in the license somewhere, but I don't really want to crawl through that... Some forum comments implied that Vitis HLS has been used in commercial tapeouts, so if there are rules they don't seem to be very strict. We should be able to just leave it up to the user to know what they're doing.
| .. code-block:: none | ||
| vitis_hls run_hls.tcl |
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All code block directives need an empty space before the main text of the block.
| In our case, we include a ``Makefile`` to script running HLS. To generate the | ||
| verilog files using the Makefile, run: |
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Below you mention this also does the "move files to vsrc" step. So maybe I would add some extra saying "to script running HLS (as well as copying files around as explained later)"
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Can we change the naming to something like CanHavePeripheryHLSGCD. Ditto for the config. fragment name.
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Can you also mention the TODO of how to connect up to an AXI interface.
generators/hls-example/run_hls.tcl
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| @@ -0,0 +1,8 @@ | |||
| open_project -reset proj_gcd_example | |||
| add_files accel/HLSAccel.cpp | |||
generators/hls-example/run_hls.tcl
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| add_files accel/HLSAccel.cpp | ||
| set_top HLSAccelBlackBox | ||
| open_solution -reset "solution1" | ||
| set_part {xcvu9p-flgb2104-2-i} |
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Why do you need a part number? This is FPGA specific so maybe the docs should mention this RTL that is made is specific to an FPGA (with part number listed here) but can be run in RTL sim.
generators/hls-example/run_hls.tcl
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| set_top HLSAccelBlackBox | ||
| open_solution -reset "solution1" | ||
| set_part {xcvu9p-flgb2104-2-i} | ||
| create_clock -period 10 |
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I see that both the FPGA part number and the clock period should probably configurable from the makefile and piped to the Chisel.
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Super super cool! Thanks Ella! |
build.sbt
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| @@ -263,6 +263,11 @@ lazy val rocc_acc_utils = (project in file("generators/rocc-acc-utils")) | |||
| .settings(libraryDependencies ++= rocketLibDeps.value) | |||
| .settings(commonSettings) | |||
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| lazy val hls_accel = (project in file("generators/hls-example")) | |||
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I think this should go in generators/chipyard/example, instead of its own project
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