Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

[rebar] speed up simulation after first #87

Closed
wants to merge 104 commits into from
Closed

[rebar] speed up simulation after first #87

wants to merge 104 commits into from

Conversation

abejgonzalez
Copy link
Contributor

Small improvement to reduce the amount of SBT calls. Should really only be called if the utilities files change or if the directory switches from vsim to/from verisim

alonamid and others added 30 commits March 12, 2019 14:30
@alonamid @abejgonzalez
change dir structure
2def0df
@alonamid @abejgonzalez
add chisel and firrtl submodules
2e7791a
@alonamid @abejgonzalez
docs placeholder
4d62a2b
@alonamid @abejgonzalez
add toolchains
6ccb3de
@alonamid @abejgonzalez
docs placeholder
49ab106
@abejgonzalez
makefile changes/split | add scripts
8227310
@abejgonzalez
rename makefiles | move verilog rule to common.mk
2c246af
@abejgonzalez
delete .ctags (have the user put this in their home)
4fd1bfb
@abejgonzalez
default to .gitignoring all files in verisim/vsim | read verilator.mk
c364869
@abejgonzalez
find now follows symlinks
e33f2fc
@abejgonzalez
Merge pull request #54 from ucb-bar/misc-changes
87f9c14 
Makefile + Ctags
@alonamid
more docs
319d2fe
@colinschmidt
Bump barstools and re-add infer-rw for better SRAM mapping
ffee1f1
@alonamid
Merge pull request #59 from ucb-bar/rebar-srams-fix
419d412 
Bump barstools and re-add infer-rw for better SRAM mapping
@alonamid @abejgonzalez
change dir structure
31e30b2
@abejgonzalez
makefile changes/split | add scripts
eb44ae1
@abejgonzalez
rename makefiles | move verilog rule to common.mk
8b899c5
@abejgonzalez
added boom and torture | added csmith
d80acd8
@abejgonzalez
rename build.sh and move to scripts
f453693
@abejgonzalez
allow sbt runMain from sbt subproject
30ef609
@abejgonzalez
align rebar with tip of project-template master | fixes build issues
7d887b2
@abejgonzalez
update boom | match build.sbt
68b2da6
@abejgonzalez
Merge remote-tracking branch 'origin/rebar-dev-align' into boom-add
80cbdd1
@abejgonzalez
bump boom/firrtl | support building boom | update genfiles in simulat…
885c5f7 
…or to make rv32 bootrom | misc cleanup
@abejgonzalez
Update README | add shortcut to build boom
e71bf21
@abejgonzalez
Merge pull request #67 from ucb-bar/rebar-dev-align
5b8eb27 
align rebar with tip of project-template master | fixes build issues
@abejgonzalez
add firrtl dependency to build.sbt | point to different firrtl jar | …
adb8897 
…a bunch of sbt plugins
@abejgonzalez
Merge remote-tracking branch 'origin/rebar-dev' into boom-add
e8d263c
@abejgonzalez
remove debug firrtl prints
46f2cd3
@abejgonzalez
remove csmith scripts
739fcec
abejgonzalez and others added 25 commits May 11, 2019 21:13
@abejgonzalez
rename the workflow
2259952
@abejgonzalez
remove old boom references | build-toolchain rebar directory fix
1ef6876
@abejgonzalez
more renaming | proper place to git submodule update
e109831
@abejgonzalez
parallelize toolchain builds with verilator
9f7f94b
@abejgonzalez
need riscv-tools for verilator build
8f34263
@abejgonzalez
correct dependencies for runs
1a6a5ea
@abejgonzalez
store all source/collateral when moving to test run
e35d299
@abejgonzalez
add status badge for master | add ci readme | add more benchmark tests
b2d4603
@abejgonzalez
revert to smaller boom config and support in ci
e1292fd
@abejgonzalez
add small config string to config.yml
2697cdc
@abejgonzalez
make hwacha smaller
2d644f1
@abejgonzalez
use example config for hwacha (otherwise use other hwacha params)
1226591
@abejgonzalez
smaller rocket For hwacha ci
a377c52
@abejgonzalez
for now just support verilog build of hwacha (no tests run on it)
7ba56b5
@abejgonzalez
clearer job naming for verilog only hwacha
59acd68
@abejgonzalez
hwacha depends on esp-tools | support java args
deccae4
@alonamid
readthedocs config
9f4fdcc
@alonamid
readthedocs fix
04c5fcf
@alonamid
docs
2ca18a4
@alonamid
docs theme
86e2e5c
@abejgonzalez
Merge pull request #82 from ucb-bar/ci-setup
a7822e1 
CI for Rebar
@alonamid
more docs
f5c1918
@alonamid
fix docs
d091fe8
@alonamid
subtitles
e0aed90
@abejgonzalez
reduce amount of sbt calls for sim
fa1c4ae
@abejgonzalez
Copy link
Contributor Author

Wrong branch

@abejgonzalez abejgonzalez deleted the rebar-dev-utility-speedup branch May 19, 2019 07:54
jerryz123 pushed a commit that referenced this pull request Apr 19, 2023
@colinschmidt
Merge pull request #87 from ucb-bar/enable_dramsim_cmd_line_dir
b84509b 
Add constructor and parser for a dramsim ini directory from the cmd line
jerryz123 pushed a commit that referenced this pull request Apr 19, 2024
@abejgonzalez
Merge pull request #87 from ucb-bar/firrtl-1.4-remove-clk-stuff
8c93874 
Move to Chisel 3.4, Firrtl 1.4, remove .clk and .pad stuff
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers
No reviews
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
4 participants
@abejgonzalez @alonamid @colinschmidt @jerryz123