vcs: fix assertions at time 0

The 'reset' signal cannot glitch from 0 to 1 at power on.
If it does, then all the assertions in a vcs design will fire.

src/main/scala/chiseltest/simulator/ipc/VpiVerilogHarnessGenerator.scala

@@ -26,7 +26,12 @@ private[chiseltest] object VpiVerilogHarnessGenerator {
     codeBuffer.append(s"module $testbenchName;\n")
     codeBuffer.append(s"  reg $clockName = 1;\n")
     toplevel.inputs.foreach { case PinInfo(name, width, _) =>
-      codeBuffer.append(s"  reg[${width - 1}:0] $name = 0;\n")
+      if (name == "reset") {
+        // This needs to start as 1, otherwise vcs assertions fire at time 0
+        codeBuffer.append(s"  reg reset = 1;\n")
+      } else {
+        codeBuffer.append(s"  reg[${width - 1}:0] $name = 0;\n")
+      }
     }
     toplevel.outputs.foreach { case PinInfo(name, width, _) =>
       codeBuffer.append(s"  wire[${width - 1}:0] $name;\n")