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Fix issues in IPCSimulatorContext (VCS) simulations (#570)
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* Fix issues in VCS simulations

* IPCSimulatorContext: better synchronization on the logs

* TestApplicationException: changes for more useful assertion failure messages

* scalafmt

Co-authored-by: Jack Koenig <[email protected]>
(cherry picked from commit 5956488)
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mwachs5 authored and mergify[bot] committed Dec 5, 2022
1 parent 5ede0ae commit b85b676
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Showing 2 changed files with 25 additions and 7 deletions.
12 changes: 10 additions & 2 deletions src/main/scala/chiseltest/internal/GenericBackend.scala
Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,8 @@ import chiseltest.coverage.TestCoverage
import chiseltest.simulator.{SimulatorContext, StepInterrupted, StepOk}
import firrtl.AnnotationSeq

import chiseltest.simulator.ipc.TestApplicationException

import scala.collection.mutable

/** Chiseltest threaded backend using the generic SimulatorContext abstraction from [[chiseltest.simulator]] */
Expand Down Expand Up @@ -202,8 +204,14 @@ class GenericBackend[T <: Module](
thread.thread.interrupt()
}
}

tester.finish() // needed to dump VCDs + terminate any external process
try {
tester.finish() // needed to dump VCDs + terminate any external process
} catch {
case e: TestApplicationException =>
throw new ChiselAssertionError(
s"Simulator exited sooner than expected. See logs for more information about what is assumed to be a Chisel Assertion which failed."
)
}
}
if (tester.sim.supportsCoverage) {
generateTestCoverageAnnotation() +: coverageAnnotations
Expand Down
20 changes: 15 additions & 5 deletions src/main/scala/chiseltest/simulator/ipc/IPCSimulatorContext.scala
Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,14 @@ private[chiseltest] class IPCSimulatorContext(
private def startProcess(cmd: Seq[String], logs: ArrayBuffer[String], cwd: os.Path): Process = {
val processBuilder = Process(cmd, cwd = cwd.toIO)
// This makes everything written to stderr get added as lines to logs
val processLogger = ProcessLogger(println, logs += _) // don't log stdout
val processLogger = ProcessLogger(
println,
{ str =>
logs.synchronized {
logs += str
}
}
) // don't log stdout
processBuilder.run(processLogger)
}

Expand Down Expand Up @@ -108,8 +115,10 @@ private[chiseltest] class IPCSimulatorContext(
}

private def dumpLogs(): Unit = {
_logs.foreach(x => println(x))
_logs.clear()
_logs.synchronized {
_logs.foreach(x => println(x))
_logs.clear()
}
}

private def throwExceptionIfDead(exitValue: Future[Int]): Unit = {
Expand Down Expand Up @@ -380,10 +389,10 @@ private[chiseltest] class IPCSimulatorContext(
mwhile(!sendCmd(SIM_CMD.FIN)) {}
val exit = Await.result(exitValue, Duration.Inf)
println("Exit Code: %d".format(exit))
dumpLogs()
inChannel.close()
outChannel.close()
cmdChannel.close()
dumpLogs()
isRunning = false
}

Expand Down Expand Up @@ -436,4 +445,5 @@ private class Channel(cwd: os.Path, name: String) {
os.remove(cwd / name)
}

private case class TestApplicationException(exitVal: Int, lastMessage: String) extends RuntimeException(lastMessage)
private[chiseltest] case class TestApplicationException(exitVal: Int, lastMessage: String)
extends RuntimeException(lastMessage)

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