This repository has been archived by the owner on Aug 19, 2024. It is now read-only.
Bug fix for verilator backend #127
Merged
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
sequencer
requested review from
chick and
ducky64
and removed request for
chick
|
Thanks:) |
Sign up for free
to subscribe to this conversation on GitHub.
Already have an account?
Sign in.
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Currently verilator backend runs
chisel3.stage.phases.Elaboratetwice, first one is generating circuit, second is generating verilog.In first elaborate phase will leave
chisel3.internal.Builderto a wrong state, which leads to second elaborate phase throw a exception "attempted to instantiate a Module, but nothing happened".