Add Chip ID Pin #212
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Add Chip ID Pin #212
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jerryz123
reviewed
Jan 1, 2024
src/main/scala/soc/ChipIdPin.scala
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| import freechips.rocketchip.subsystem._ | ||
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| case class ChipIdPinParams ( | ||
| numChips: Int = 1, |
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Instead of numChips, lets just make this width. Everything is in relation to the width.
jerryz123
reviewed
Jan 1, 2024
src/main/scala/soc/ChipIdPin.scala
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| val inner_io = tlbus { | ||
| val node = TLRegisterNode( | ||
| address = Seq(AddressSet(params.chipIdAddr, 0xfff)), //TODO: fix address set size |
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Lets make the address set size 4096 bytes, to match all the other devices.
A wider size than the actual register also simplifies address decoding.
jerryz123
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Jan 1, 2024
added 2 commits
January 12, 2024 10:36
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jerryz123
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Jan 16, 2024
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Adds a pin to set the chip id for each chip. The pin drives a read-only MMIO register attached to the CBUS.
The purpose of adding this pin is to enable cache coherency across multi-chip configs in Chipyard.