Verilog: support virtual interface variables #3720
Conversation
Codecov ReportPatch coverage:
Additional details and impacted files@@ Coverage Diff @@
## master #3720 +/- ##
==========================================
- Coverage 82.99% 82.98% -0.02%
==========================================
Files 226 226
Lines 54972 55003 +31
==========================================
+ Hits 45626 45645 +19
- Misses 9346 9358 +12
☔ View full report in Codecov by Sentry. |
parsers/verilog.c
Outdated
| @@ -132,6 +133,7 @@ typedef struct sTokenInfo { | |||
| bool classScope; /* Context is local to the current sub-context */ | |||
| bool parameter; /* parameter which can be overridden */ | |||
| bool hasParamList; /* module definition has a parameter port list */ | |||
| bool virtual; /* has virtual */ | |||
There was a problem hiding this comment.
I don't care about whitespaces in code that I don't maintain directly.
However, you can care:-).
If you use Emacs, M-x whitespace-mode helps you see how the sequence of whitespace is made.
There was a problem hiding this comment.
@masatake san,
However, you can care:-).
Sorry. I have been caring about it.
The indentation rules for this project are different from those I usually use.
I worked on a new PC that had not yet been configured for this project. I wrongly indented the code by hand and committed it.
I have corrected the original commit.
I was also concerned about the inconsistent use of spaces in the indentation. I took this opportunity to add a commit that fixes that as well.
Could you review it again?
There was a problem hiding this comment.
About the spacing style(?), I don't have a strong preference.
If the file's maintainer feels comfortable, that's good.
As a reference, we have .editorconfig globally used in our code base.
If you have not introduced editorconfig on your new PC, this will be a good time to introduce it.
I have adjusted the spacing style for only a few files in our source tree because such an adjustment may make 'git bisect' harder.
Signed-off-by: Hiroo HAYASHI <[email protected]>
Signed-off-by: Hiroo HAYASHI <[email protected]>
hirooih
force-pushed
the
verilog-virtual-interface
branch
from
55bfbe4
to
ebb1bde
Compare
|
Thank you for your reviewing. |
virtual interfaceis a variable. But the Verilog parser mistakenly declared it as an interface.This PR fixes the issue.