Feature: missing MIPS rewriters

uxmal · Jul 15, 2024 · e975553 · e975553
1 parent fee2293
commit e975553
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Showing 4 changed files with 385 additions and 348 deletions.
diff --git a/src/Arch/Mips/MipsRewriter.Alu.cs b/src/Arch/Mips/MipsRewriter.Alu.cs
@@ -384,14 +384,18 @@ private void RewriteLx(MipsInstruction instr, PrimitiveType dt, int scale)
             m.Assign(dst, src);
         }
 
-        private void RewriteMac_int(MipsInstruction instr, Func<Expression,Expression,Expression> fn)
+        private void RewriteMac_int(
+            MipsInstruction instr,
+            DataType dtProduct,
+            BinaryOperator mul,
+            BinaryOperator acc)
         {
             var op1 = RewriteOperand0(instr.Operands[0]);
             var op2 = RewriteOperand0(instr.Operands[1]);
             var hi_lo = binder.EnsureSequence(PrimitiveType.Word64, arch.hi, arch.lo);
-            var product = m.IMul(op1, op2);
+            var product = m.Bin(mul, dtProduct, op1, op2);
             product.DataType = hi_lo.DataType;
-            m.Assign(hi_lo, fn(hi_lo, product));
+            m.Assign(hi_lo, m.Bin(acc, hi_lo, product));
         }
 
         private void RewriteMf(MipsInstruction instr, RegisterStorage reg)

diff --git a/src/Arch/Mips/MipsRewriter.cs b/src/Arch/Mips/MipsRewriter.cs
@@ -198,7 +198,8 @@ public IEnumerator<RtlInstructionCluster> GetEnumerator()
                 case Mnemonic.lwl: RewriteLwl(instr); break;
                 case Mnemonic.lwr: RewriteLwr(instr); break;
                 case Mnemonic.lwu: RewriteLoad(instr, PrimitiveType.UInt32); break;
-                case Mnemonic.madd: RewriteMac_int(instr, m.IAdd); break;
+                case Mnemonic.madd: RewriteMac_int(instr, PrimitiveType.Int64, Operator.SMul, Operator.IAdd); break;
+                case Mnemonic.maddu: RewriteMac_int(instr, PrimitiveType.UInt64, Operator.UMul, Operator.IAdd); break;
                 case Mnemonic.madd_s: RewriteMac_real(instr, PrimitiveType.Real32, m.FAdd); break;
                 case Mnemonic.madd_ps: RewriteMac_vec(instr, PrimitiveType.Real32, m.FAdd); break;
                 case Mnemonic.mfc0: RewriteMfc0(instr); break;
@@ -214,7 +215,8 @@ public IEnumerator<RtlInstructionCluster> GetEnumerator()
                 case Mnemonic.movz: RewriteMovCc(instr, m.Eq0); break;
                 case Mnemonic.mov_d: RewriteCopy(instr); break;
                 case Mnemonic.mov_s: RewriteCopy(instr); break;
-                case Mnemonic.msub: RewriteMac_int(instr, m.ISub); break;
+                case Mnemonic.msub: RewriteMac_int(instr, PrimitiveType.Int64, Operator.SMul, Operator.ISub); break;
+                case Mnemonic.msubu: RewriteMac_int(instr, PrimitiveType.UInt64, Operator.UMul, Operator.ISub); break;
                 case Mnemonic.msub_s: RewriteMac_real(instr, PrimitiveType.Real32, m.FSub); break;
                 case Mnemonic.mtc1: RewriteMtc1(instr); break;
                 case Mnemonic.mul: RewriteMul(instr, m.SMul, PrimitiveType.Int32); break;
@@ -240,6 +242,7 @@ public IEnumerator<RtlInstructionCluster> GetEnumerator()
                 case Mnemonic.sdc1: RewriteStore(instr); break;
                 case Mnemonic.sdc2: RewriteSdc2(instr); break;
                 case Mnemonic.sdl: RewriteSdl(instr); break;
+                case Mnemonic.sdxc1: RewriteStore(instr); break;
                 case Mnemonic.sdr: RewriteSdr(instr); break;
                 case Mnemonic.seb: RewriteSignExtend(instr, PrimitiveType.Byte); break;
                 case Mnemonic.seh: RewriteSignExtend(instr, PrimitiveType.Word16); break;

diff --git a/src/UnitTests/Arch/Mips/MipsRewriterTests.cs b/src/UnitTests/Arch/Mips/MipsRewriterTests.cs
@@ -1277,15 +1277,33 @@ public void MipsRw_madd()
         {
             AssertCode(0x71A60000,   // madd	r13,r6
                 "0|L--|00100000(4): 1 instructions",
-                "1|L--|hi_lo = hi_lo + r13 *64 r6");
+                "1|L--|hi_lo = hi_lo + r13 *s64 r6");
+        }
+
+        [Test]
+        public void MipsRw_maddu()
+        {
+            Given_HexString("70000001");
+            AssertCode(     // maddu    r0,r0
+                "0|L--|00100000(4): 1 instructions",
+                "1|L--|hi_lo = hi_lo + 0<32> *u64 0<32>");
         }
 
         [Test]
         public void MipsRw_msub()
         {
             AssertCode(0x71670004,   // msub	r11,r7
                 "0|L--|00100000(4): 1 instructions",
-                "1|L--|hi_lo = hi_lo - r11 *64 r7");
+                "1|L--|hi_lo = hi_lo - r11 *s64 r7");
+        }
+
+        [Test]
+        public void MipsRw_msubu()
+        {
+            Given_HexString("70000005");
+            AssertCode(     // msubu    r0,r0
+                "0|L--|00100000(4): 1 instructions",
+                "1|L--|hi_lo = hi_lo - 0<32> *u64 0<32>");
         }
 
         [Test]
@@ -1329,6 +1347,15 @@ public void MipsRw_sdc2()
                 "1|L--|Mem0[sp - 0x44BA<32>:word64] = __read_cpr2<word64>(0x18<8>)");
         }
 
+        [Test]
+        public void MipsRw_sdxc1()
+        {
+            Given_HexString("4E414D49");
+            AssertCode(     // sdxc1    f9,r1(r18)
+                "0|L--|00100000(4): 1 instructions",
+                "1|L--|Mem0[r18 + r1:word64] = f9");
+        }
+
         [Test]
         public void MipsRw_swc2()
         {