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RISC-V: c.slli64, c.srai64 & c.srli64 instructions #1328

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Feb 9, 2024
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RISC-V: c.slli64, c.srai64 & c.srli64 instructions #1328

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15 changes: 12 additions & 3 deletions src/Arch/RiscV/InstructionSet.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -731,8 +731,14 @@ public Decoder[] CreateRootDecoders()
Instr(Mnemonic.c_lui, R(7), ImmShS(12, bf_12_1_2_5))),

new MaskDecoder(10, 2, "comp1",
Instr(Mnemonic.c_srli, Rc(7), Imm(bf_12_1_2_5)),
Instr(Mnemonic.c_srai, Rc(7), Imm(bf_12_1_2_5)),
Select(bf_12_1_2_5, u => u == 0, "",
Instr(Mnemonic.c_srli64, Rc(7)),
Instr(Mnemonic.c_srli, Rc(7), Imm(bf_12_1_2_5))
),
Select(bf_12_1_2_5, u => u == 0, "",
Instr(Mnemonic.c_srai64, Rc(7)),
Instr(Mnemonic.c_srai, Rc(7), Imm(bf_12_1_2_5))
),
Instr(Mnemonic.c_andi, Rc(7), ImmS(bf_12_1_2_5)),
new MaskDecoder(12, 1, "comp1_1",
new MaskDecoder(5, 2, "comp1_1_1",
Expand All @@ -757,7 +763,10 @@ public Decoder[] CreateRootDecoders()

var compressed10 = new Decoder[8]
{
Instr(Mnemonic.c_slli, R_nz(7), ImmB(bf_12_1_2_5)),
Select(bf_12_1_2_5, u => u == 0, "",
Instr(Mnemonic.c_slli64, R_nz(7)),
Instr(Mnemonic.c_slli, R_nz(7), ImmB(bf_12_1_2_5))
),
WordSize(
rv32: FpInstr64(Mnemonic.c_fldsp, F(7), MemcSpRel(PrimitiveType.Word64, bf_2_3_12_1_5_2)),
rv64: FpInstr64(Mnemonic.c_fldsp, F(7), MemcSpRel(PrimitiveType.Word64, bf_2_3_12_1_5_2)),
Expand Down
3 changes: 3 additions & 0 deletions src/Arch/RiscV/Mnemonic.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -91,8 +91,11 @@ public enum Mnemonic
c_sd,
c_sdsp,
c_slli,
c_slli64,
c_srai,
c_srai64,
c_srli,
c_srli64,
c_sub,
c_subw,
c_sw,
Expand Down
3 changes: 3 additions & 0 deletions src/Arch/RiscV/RiscVRewriter.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -146,8 +146,11 @@ public IEnumerator<RtlInstructionCluster> GetEnumerator()
case Mnemonic.c_nop: m.Nop(); break;
case Mnemonic.c_or: RewriteCompressedBinOp(Operator.Or); break;
case Mnemonic.c_slli: RewriteCompressedBinOp(SllI); break;
case Mnemonic.c_slli64: m.Nop(); break;
case Mnemonic.c_srai: RewriteCompressedBinOp(SraI); break;
case Mnemonic.c_srai64: m.Nop(); break;
case Mnemonic.c_srli: RewriteCompressedBinOp(SrlI); break;
case Mnemonic.c_srli64: m.Nop(); break;
case Mnemonic.c_sub: RewriteCompressedBinOp(Operator.ISub); break;
case Mnemonic.c_sd: RewriteStore(PrimitiveType.Word64); break;
case Mnemonic.c_sdsp: RewriteStore(PrimitiveType.Word64); break;
Expand Down
18 changes: 17 additions & 1 deletion src/UnitTests/Arch/RiscV/RiscVDisassemblerTests.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -680,12 +680,24 @@ public void RiscV_dasm_c_srli()
AssertCode("c.srli\ta5,0xA", 0x000083A9);
}

[Test]
public void RiscV_dasm_c_srli64()
{
AssertCode("c.srli64\ta2", 0x00008201);
}

[Test]
public void RiscV_dasm_c_srai()
{
AssertCode("c.srai\ta4,0x3F", 0x0000977D);
}

[Test]
public void RiscV_dasm_c_srai64()
{
AssertCode("c.srai64\ta3", 0x00008681);
}

[Test]
public void RiscV_dasm_c_andi()
{
Expand All @@ -704,7 +716,11 @@ public void RiscV_dasm_c_slli()
AssertCode("c.slli\ts0,0x3", 0x0000040E);
}


[Test]
public void RiscV_dasm_c_slli64()
{
AssertCode("c.slli64\ta5", 0x00000782);
}

[Test]
public void RiscV_dasm_sll()
Expand Down
27 changes: 27 additions & 0 deletions src/UnitTests/Arch/RiscV/RiscVRewriterTests.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -747,6 +747,15 @@ public void RiscV_rw_c_slli()
"1|L--|s0 = s0 << 3<i32>");
}

[Test]
public void RiscV_rw_c_slli64()
{
Given_RiscVInstructions(0x00000782); // c.slli64\ta5
AssertCode(
"0|L--|0000000000010000(2): 1 instructions",
"1|L--|nop");
}

[Test]
public void RiscV_rw_c_srai()
{
Expand All @@ -756,6 +765,15 @@ public void RiscV_rw_c_srai()
"1|L--|a4 = a4 >> 63<i32>");
}

[Test]
public void RiscV_rw_c_srai64()
{
Given_RiscVInstructions(0x00008681); // c.srai64\ta3
AssertCode(
"0|L--|0000000000010000(2): 1 instructions",
"1|L--|nop");
}

[Test]
public void RiscV_rw_c_srli()
{
Expand All @@ -765,6 +783,15 @@ public void RiscV_rw_c_srli()
"1|L--|a5 = a5 >>u 10<i32>");
}

[Test]
public void RiscV_rw_c_srli64()
{
Given_RiscVInstructions(0x00008201); // c.srli64\ta2
AssertCode(
"0|L--|0000000000010000(2): 1 instructions",
"1|L--|nop");
}

[Test]
public void RiscV_rw_c_sub()
{
Expand Down
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