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TRIUMF
- Vancouver, BC, Canada
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Mersenne-Twister-HLS
Mersenne-Twister-HLS PublicHigh Level Synthesis (Xilinx HLS) implementation of the popular Mersenne Twister pseudo-random number generator. This will generate a VHDL/Verilog module that streams 32 bit psuedo-randoms at 500 M…
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Science_Week_ML_tutorial
Science_Week_ML_tutorial Publicnotebooks and code for the ML hands-on session during TRIUMF Science Week 2019
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Batcher-Even-Odd-mergesort-in-RTL
Batcher-Even-Odd-mergesort-in-RTL PublicCode sample of sorting algorithm implemented at RTL level in VHDL. The bulk of the code was actually created by my script.
VHDL 1
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UVicWorkshopPlayground
UVicWorkshopPlayground PublicForked from WatChMaL/UVicWorkshopPlayground
Workspace for UVic April 2019 Workshop Participants
Jupyter Notebook 1
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