fix(rp2040): adcs adding 0+0 with carry shouldn't set overflow

wokwi · May 14, 2021 · 2342ce2 · 2342ce2
1 parent 29970d0
commit 2342ce2
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Showing 2 changed files with 14 additions and 1 deletion.
diff --git a/src/instructions.spec.ts b/src/instructions.spec.ts
@@ -151,6 +151,19 @@ describe('Cortex-M0+ Instruction Set', () => {
     expect(registers.V).toEqual(true);
   });
 
+  it('should not set the overflow flag when executing `adcs r3, r2` adding 0 to 0 with carry', async () => {
+    await cpu.setPC(0x20000000);
+    await cpu.writeUint16(0x20000000, opcodeADCS(r3, r2));
+    cpu.setRegisters({ r2: 0, r3: 0, C: true, Z: true });
+    await cpu.singleStep();
+    const registers = await cpu.readRegisters();
+    expect(registers.r3).toEqual(1);
+    expect(registers.N).toEqual(false);
+    expect(registers.Z).toEqual(false);
+    expect(registers.C).toEqual(false);
+    expect(registers.V).toEqual(false);
+  });
+
   it('should execute a `add sp, 0x10` instruction', async () => {
     await cpu.setPC(0x20000000);
     await cpu.setRegisters({ sp: 0x10000040 });

diff --git a/src/rp2040.ts b/src/rp2040.ts
@@ -823,7 +823,7 @@ export class RP2040 {
       this.C = result > 0xffffffff;
       this.V =
         ((leftValue | 0) >= 0 && (rightValue | 0) >= 0 && (result | 0) < 0) ||
-        ((leftValue | 0) <= 0 && (rightValue | 0) <= 0 && (result | 0) > 0);
+        ((leftValue | 0) < 0 && (rightValue | 0) < 0 && (result | 0) > 0);
     }
     // ADD (register = SP plus immediate)
     else if (opcode >> 11 === 0b10101) {