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Small suggestion about PC #1
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Thank you! Regarding PC, the I found that the ARM® v6-M manual explains it in section A4.2.1 (Use of labels in UAL instruction syntax):
I will incorporate that into the code in our next session on Tuesday. |
Just as reminder (A.5.1.2):
Which works when you increment PC before execute instruction. |
I'm wondering why it uses "current instruction + 4" as the baseline, as instructions are only 2 bytes large (other than BL if I'm not wrong). It seems like even if we pre-increment, we'll have to add 2 to the value of PC when we are using it in offset-relative calculations |
It is exactly the same you posted earlier, just described with different words:
It is aligned PC only for few instructions, like ADR or LDR, but again, i played a bit with your code today and it works only when PC is incemented before instruction is excuted. Incementing PC at top is fixing also the problem with of course you dont need this line, which is moved into top: |
Thumb instructions are only 2-bytes long, but after a |
Interestingly, in non-Thumb mode it's actually PC+8: "The PC value of an instruction is its address plus 4 for a Thumb instruction, or plus 8 for an ARM instruction." |
Ah! On this ARM variant, PC actually points 2 instructions after the current one, because they deepened the pipeline from 3- to 5-stages. It surprises me that they chose to expose this extra 1 instruction offset. DEC/Intel's StrongARM also had a similar 5-stage pipeline, but still only a +1 instruction offset in PC. |
Cool, thanks for the link! |
Thanks again for the suggestion, @chegewara! I ended up implementing it at the beginning of last week's stream, and it actually helped fixed the bug we were looking at. So great timing too :-) |
No problem, and i saw last video. I will watch whole series, because its very nice and even if i dont plan to use it, most likely, it is very good to learn new things and new way of thinking. Good luck. |
new instructions: ADR, BICS, BLX, BX (thanks Tony #1), LDRH, POP, STMIA. next time, we need to implement: - 4198 sbcs r0, r3 - 4643 mov r3, r8 - 4005 ands r5, r0
Hi, i really like how you are explaining and doing all this stuff, but i think you have 1 wrong assumption.
PC should be increased
before
instruction is parsed/exacuted:https://github.com/wokwi/rp2040js/blob/master/src/rp2040.ts#L151
This will let you fix the branch tests:
For confirmation here is pseudocode for BL:
As you can see next instruction address store is PC, which cant be PC to currently running instruction or this will stuck in recurent loop.
Another small suggestion about finding the right instruction in datasheet, you can use hex calculator.
This snippet is good too to sign extend any value, like imm5, imm8, imm11:
Thanks
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