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fix(rp2040): Fix SBCS flags handling #30

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May 16, 2021
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13 changes: 13 additions & 0 deletions src/instructions.spec.ts
Original file line number Diff line number Diff line change
Expand Up @@ -1055,6 +1055,19 @@ describe('Cortex-M0+ Instruction Set', () => {
expect(registers.V).toEqual(false);
});

it('should execute a `sbcs r0, r3` instruction', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint16(0x20000000, opcodeSBCS(r0, r3));
await cpu.setRegisters({ r0: 0, r3: 0xffffffff, C: false });
await cpu.singleStep();
const registers = await cpu.readRegisters();
expect(registers.r0).toEqual(0);
expect(registers.N).toEqual(false);
expect(registers.Z).toEqual(true);
expect(registers.C).toEqual(false);
expect(registers.V).toEqual(false);
});

it('should execute a `sdmia r0!, {r1, r2}` instruction', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint16(0x20000000, opcodeSTMIA(r0, (1 << r1) | (1 << r2)));
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6 changes: 3 additions & 3 deletions src/rp2040.ts
Original file line number Diff line number Diff line change
Expand Up @@ -1410,16 +1410,16 @@ export class RP2040 {
else if (opcode === 0b1011111100000000) {
// Do nothing!
}
// SBCS (Encoding T2)
// SBCS (Encoding T1)
else if (opcode >> 6 === 0b0100000110) {
const Rm = (opcode >> 3) & 0x7;
const Rdn = opcode & 0x7;
const operand1 = this.registers[Rdn];
const operand2 = this.registers[Rm] + (this.C ? 0 : 1);
const result = (operand1 - operand2) | 0;
this.registers[Rdn] = result;
this.N = operand1 < operand2;
this.Z = operand1 === operand2;
this.N = (operand1 | 0) < (operand2 | 0);
this.Z = (operand1 | 0) === (operand2 | 0);
this.C = operand1 >= operand2;
this.V = (operand1 | 0) < 0 && operand2 > 0 && result > 0;
}
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