feat(sio): fix implemented Hardware Divider

src/peripherals/reset.ts

@@ -0,0 +1,37 @@
+import { BasePeripheral, Peripheral } from './peripheral';
+
+const RESET = 0x0; //Reset control.
+const WDSEL = 0x4; //Watchdog select.
+const RESET_DONE = 0x8; //Reset Done
+
+export class RPReset extends BasePeripheral implements Peripheral {
+  private reset: number = 0;
+  private wdsel: number = 0;
+  private reset_done: number = 0x1ffffff;
+
+  readUint32(offset: number) {
+    switch (offset) {
+      case RESET:
+        return this.reset;
+      case WDSEL:
+        return this.wdsel;
+      case RESET_DONE:
+        return this.reset_done;
+    }
+    return super.readUint32(offset);
+  }
+
+  writeUint32(offset: number, value: number) {
+    switch (offset) {
+      case RESET:
+        this.reset = value & 0x1ffffff;
+        break;
+      case WDSEL:
+        this.wdsel = value & 0x1ffffff;
+        break;
+      default:
+        super.writeUint32(offset, value);
+        break;
+    }
+  }
+}

src/rp2040.ts

@@ -7,6 +7,7 @@ import { RP2040SysCfg } from './peripherals/syscfg';
 import { RPTimer } from './peripherals/timer';
 import { RPUART } from './peripherals/uart';
 import { RPSIO } from './sio';
+import { RPReset } from './peripherals/reset';
 
 export const FLASH_START_ADDRESS = 0x10000000;
 export const FLASH_END_ADDRESS = 0x14000000;
@@ -191,7 +192,7 @@ export class RP2040 {
     0x40000: new UnimplementedPeripheral(this, 'SYSINFO_BASE'),
     0x40004: new RP2040SysCfg(this, 'SYSCFG'),
     0x40008: new UnimplementedPeripheral(this, 'CLOCKS_BASE'),
-    0x4000c: new UnimplementedPeripheral(this, 'RESETS_BASE'),
+    0x4000c: new RPReset(this, 'RESETS_BASE'),
     0x40010: new UnimplementedPeripheral(this, 'PSM_BASE'),
     0x40014: new UnimplementedPeripheral(this, 'IO_BANK0_BASE'),
     0x40018: new UnimplementedPeripheral(this, 'IO_QSPI_BASE'),

src/sio.spec.ts

@@ -0,0 +1,64 @@
+import { RP2040, SIO_START_ADDRESS } from './rp2040';
+
+//HARDWARE DIVIDER
+const _DIV_UDIVIDEND = SIO_START_ADDRESS + 0x060; //  Divider unsigned dividend
+const _DIV_UDIVISOR = SIO_START_ADDRESS + 0x064; //  Divider unsigned divisor
+const _DIV_SDIVIDEND = SIO_START_ADDRESS + 0x068; //  Divider signed dividend
+const _DIV_SDIVISOR = SIO_START_ADDRESS + 0x06c; //  Divider signed divisor
+const _DIV_QUOTIENT = SIO_START_ADDRESS + 0x070; //  Divider result quotient
+const _DIV_REMAINDER = SIO_START_ADDRESS + 0x074; //Divider result remainder
+const _DIV_CSR = SIO_START_ADDRESS + 0x078;
+
+describe('RPSIO', () => {
+  describe('Hardware Divider', () => {
+    it('should set perform a signed hardware divider 123456 / -321 = -384 R192', () => {
+      const rp2040 = new RP2040();
+      expect(rp2040.readUint32(_DIV_CSR)).toEqual(0);
+      rp2040.writeUint32(_DIV_SDIVIDEND, 123456);
+      rp2040.writeUint32(_DIV_SDIVISOR, -321);
+      expect(rp2040.readUint32(_DIV_CSR)).toEqual(1);
+      expect(rp2040.readUint32(_DIV_REMAINDER)).toEqual(192);
+      expect(rp2040.readUint32(_DIV_QUOTIENT)).toEqual(-384);
+      expect(rp2040.readUint32(_DIV_CSR)).toEqual(0);
+    });
+
+    it('should set perform an unsigned hardware divider 123456 / 321 = 384 R192', () => {
+      const rp2040 = new RP2040();
+      expect(rp2040.readUint32(_DIV_CSR)).toEqual(0);
+      rp2040.writeUint32(_DIV_UDIVIDEND, 123456);
+      const cycles = rp2040.cycles;
+      rp2040.writeUint32(_DIV_UDIVISOR, 321);
+      expect(rp2040.cycles - cycles).toEqual(8);
+      expect(rp2040.readUint32(_DIV_CSR)).toEqual(1);
+      expect(rp2040.readUint32(_DIV_REMAINDER)).toEqual(192);
+      expect(rp2040.readUint32(_DIV_QUOTIENT)).toEqual(384);
+      expect(rp2040.readUint32(_DIV_CSR)).toEqual(0);
+    });
+
+    it('should perform a division, store the result, do another division then restore the previously stored result ', () => {
+      const rp2040 = new RP2040();
+      rp2040.writeUint32(_DIV_SDIVIDEND, 123456);
+      rp2040.writeUint32(_DIV_SDIVISOR, -321);
+      const remainder = rp2040.readUint32(_DIV_REMAINDER);
+      const quotient = rp2040.readUint32(_DIV_QUOTIENT);
+      expect(remainder).toEqual(192);
+      expect(quotient).toEqual(-384);
+      rp2040.writeUint32(_DIV_UDIVIDEND, 123);
+      rp2040.writeUint32(_DIV_UDIVISOR, 7);
+      expect(rp2040.readUint32(_DIV_REMAINDER)).toEqual(4);
+      expect(rp2040.readUint32(_DIV_QUOTIENT)).toEqual(17);
+      rp2040.writeUint32(_DIV_REMAINDER, remainder);
+      rp2040.writeUint32(_DIV_QUOTIENT, quotient);
+      expect(rp2040.readUint32(_DIV_REMAINDER)).toEqual(192);
+      expect(rp2040.readUint32(_DIV_QUOTIENT)).toEqual(-384);
+    });
+
+    it('should set perform an unsigned division by zero 123456 / 0 = Infinity RNaN', () => {
+      const rp2040 = new RP2040();
+      rp2040.writeUint32(_DIV_UDIVIDEND, 123456);
+      rp2040.writeUint32(_DIV_UDIVISOR, 0);
+      expect(rp2040.readUint32(_DIV_REMAINDER)).toEqual(NaN);
+      expect(rp2040.readUint32(_DIV_QUOTIENT)).toEqual(Infinity);
+    });
+  });
+});

src/sio.ts

@@ -24,11 +24,25 @@ const GPIO_HI_OE_XOR = 0x04c; // QSPI output enable XOR
 
 const GPIO_MASK = 0x3fffffff;
 
+//HARDWARE DIVIDER
+const DIV_UDIVIDEND = 0x060; //  Divider unsigned dividend
+const DIV_UDIVISOR = 0x064; //  Divider unsigned divisor
+const DIV_SDIVIDEND = 0x068; //  Divider signed dividend
+const DIV_SDIVISOR = 0x06c; //  Divider signed divisor
+const DIV_QUOTIENT = 0x070; //  Divider result quotient
+const DIV_REMAINDER = 0x074; //Divider result remainder
+const DIV_CSR = 0x078;
+
 export class RPSIO {
   gpioValue = 0;
   gpioOutputEnable = 0;
   qspiGpioValue = 0;
   qspiGpioOutputEnable = 0;
+  divDividend = 0;
+  divDivisor = 1;
+  divQuotient = 0;
+  divRemainder = 0;
+  divCSR = 0;
 
   constructor(private readonly rp2040: RP2040) {}
 
@@ -62,6 +76,19 @@ export class RPSIO {
       case CPUID:
         // Returns the current CPU core id (always 0 for now)
         return 0;
+      case DIV_UDIVIDEND:
+      case DIV_SDIVIDEND:
+        return this.divDividend;
+      case DIV_UDIVISOR:
+      case DIV_SDIVISOR:
+        return this.divDivisor;
+      case DIV_QUOTIENT:
+        this.divCSR = 0;
+        return this.divQuotient;
+      case DIV_REMAINDER:
+        return this.divRemainder;
+      case DIV_CSR:
+        return this.divCSR;
     }
     console.warn(`Read from invalid SIO address: ${offset.toString(16)}`);
     return 0xffffffff;
@@ -117,6 +144,28 @@ export class RPSIO {
       case GPIO_HI_OE_XOR:
         this.qspiGpioOutputEnable ^= value & GPIO_MASK;
         break;
+      case DIV_UDIVIDEND:
+      case DIV_SDIVIDEND:
+        this.divDividend = value | 0;
+        this.divCSR = 1;
+        this.divQuotient = Math.trunc(this.divDividend / this.divDivisor);
+        this.divRemainder = Math.trunc(this.divDividend % this.divDivisor);
+        this.rp2040.cycles += 8;
+        break;
+      case DIV_UDIVISOR:
+      case DIV_SDIVISOR:
+        this.divDivisor = value | 0;
+        this.divCSR = 1;
+        this.divQuotient = Math.trunc(this.divDividend / this.divDivisor);
+        this.divRemainder = Math.trunc(this.divDividend % this.divDivisor);
+        this.rp2040.cycles += 8;
+        break;
+      case DIV_QUOTIENT:
+        this.divQuotient = value | 0;
+        break;
+      case DIV_REMAINDER:
+        this.divRemainder = value | 0;
+        break;
     }
   }
 }