backend: (riscv) Add StaticInsnsRepresentation and implement it for d…

…ma ops

xdsl/backend/riscv/traits.py

@@ -0,0 +1,21 @@
+from xdsl.ir import Operation
+from xdsl.traits import HasInsnsRepresentation
+
+
+class StaticInsnsRepresentation(HasInsnsRepresentation):
+    """
+    Returns the first parameter as an insn template string.
+
+    See https://sourceware.org/binutils/docs/as/RISC_002dV_002dDirectives.html for more information
+    """
+
+    def get_insn(self, op: Operation) -> str:
+        """
+        Return the insns representation of the operation for printing.
+        """
+        insn_str = self.parameters
+        if not isinstance(insn_str, str):
+            raise ValueError(
+                "Paramter of StaticInsnsRepresentation must be the insn string"
+            )
+        return insn_str

xdsl/dialects/riscv_snitch.py

@@ -5,6 +5,7 @@
 
 from typing_extensions import Self
 
+from xdsl.backend.riscv.traits import StaticInsnsRepresentation
 from xdsl.dialects import riscv, stream
 from xdsl.dialects.builtin import (
     IntAttr,
@@ -462,6 +463,8 @@ class DMSourceOp(IRDLOperation, RISCVInstruction):
     ptrlo = operand_def(riscv.IntRegisterType)
     ptrhi = operand_def(riscv.IntRegisterType)
 
+    traits = frozenset([StaticInsnsRepresentation(".insn r 0x2b, 0, 0, x0, {0}, {1}")])
+
     def __init__(self, ptrlo: SSAValue | Operation, ptrhi: SSAValue | Operation):
         super().__init__(operands=[ptrlo, ptrhi])
 
@@ -476,6 +479,8 @@ class DMDestinationOp(IRDLOperation, RISCVInstruction):
     ptrlo = operand_def(riscv.IntRegisterType)
     ptrhi = operand_def(riscv.IntRegisterType)
 
+    traits = frozenset([StaticInsnsRepresentation(".insn r 0x2b, 0, 1, x0, {0}, {1}")])
+
     def __init__(self, ptrlo: SSAValue | Operation, ptrhi: SSAValue | Operation):
         super().__init__(operands=[ptrlo, ptrhi])
 
@@ -490,6 +495,8 @@ class DMStrideOp(IRDLOperation, RISCVInstruction):
     srcstrd = operand_def(riscv.IntRegisterType)
     dststrd = operand_def(riscv.IntRegisterType)
 
+    traits = frozenset([StaticInsnsRepresentation(".insn r 0x2b, 0, 6, x0, {0}, {1}")])
+
     def __init__(self, srcstrd: SSAValue | Operation, dststrd: SSAValue | Operation):
         super().__init__(operands=[srcstrd, dststrd])
 
@@ -503,6 +510,8 @@ class DMRepOp(IRDLOperation, RISCVInstruction):
 
     reps = operand_def(riscv.IntRegisterType)
 
+    traits = frozenset([StaticInsnsRepresentation(".insn r 0x2b, 0, 7, x0, {0}, x0")])
+
     def __init__(self, reps: SSAValue | Operation):
         super().__init__(operands=[reps])
 
@@ -518,6 +527,8 @@ class DMCopyOp(IRDLOperation, RISCVInstruction):
     size = operand_def(riscv.IntRegisterType)
     config = operand_def(riscv.IntRegisterType)
 
+    traits = frozenset([StaticInsnsRepresentation(".insn r 0x2b, 0, 3, {0}, {1}, {2}")])
+
     def __init__(
         self,
         size: SSAValue | Operation,
@@ -537,6 +548,8 @@ class DMStatOp(IRDLOperation, RISCVInstruction):
     dest = result_def(riscv.IntRegisterType)
     status = operand_def(riscv.IntRegisterType)
 
+    traits = frozenset([StaticInsnsRepresentation(".insn r 0x2b, 0, 5, {0}, {1}, {2}")])
+
     def __init__(
         self,
         status: SSAValue | Operation,
@@ -556,6 +569,8 @@ class DMCopyImmOp(IRDLOperation, RISCVInstruction):
     size = operand_def(riscv.IntRegisterType)
     config = prop_def(UImm5Attr)
 
+    traits = frozenset([StaticInsnsRepresentation(".insn r 0x2b, 0, 2, {0}, {1}, {2}")])
+
     def __init__(
         self,
         size: SSAValue | Operation,
@@ -606,6 +621,8 @@ class DMStatImmOp(IRDLOperation, RISCVInstruction):
     dest = result_def(riscv.IntRegisterType)
     status = prop_def(UImm5Attr)
 
+    traits = frozenset([StaticInsnsRepresentation(".insn r 0x2b, 0, 4, {0}, {1}, {2}")])
+
     def __init__(
         self,
         status: int | UImm5Attr,