LF-3103 phy: freescale: pcie: fix the imx8mp evk ep rc link degrade i…

…ssue

Refine commit 17db82300f80 ("MLK-25089 phy: freescale: pcie: fix the
imx8mp evk ep rc link speed issue")
Fine tune the PHY parameters, let the PCIe link up to GEN3 between two
i.MX865 EVK boards in the i.MX EP RC validation system.

Since this fine tuned is only specified for EVK boards. Add the command
parameter to specify it when do the EP RC tests between two i.MX8MP EVK
boards. Use the "pcie_phy_tuned=yes" to enable the PHY fine-tune.

Signed-off-by: Richard Zhu <[email protected]>
Reviewed-by: Peter Chen <[email protected]>
(cherry picked from commit 2ab5581a1448bf24a37f8082ffe725a54ce09b5e)

drivers/phy/freescale/phy-fsl-imx8-pcie.c

@@ -62,6 +62,7 @@
 #define IMX8MP_PCIE_PHY_TRSV_REG206	0x738
 #define  LN0_TG_RX_SIGVAL_LBF_DELAY	0x4
 
+static int imx8_pcie_phy_tuned;
 struct imx8_pcie_phy {
 	struct phy *phy;
 	struct clk *clk;
@@ -135,34 +136,36 @@ static int imx8_pcie_phy_cal(struct phy *phy)
 	 * Fine tune the parameters of the PHY, let PCIe link up to GEN3
 	 * between two EVK boards in the EP/RC validation system.
 	 */
-	writel(LN0_OVRD_TX_DRV_LVL,
-	       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG001);
-	writel(LN0_OVRD_TX_DRV_PST_LVL_G1,
-	       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG005);
-	writel(LN0_OVRD_TX_DRV_PST_LVL_G2,
-	       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG006);
-	writel(LN0_OVRD_TX_DRV_PST_LVL_G3,
-	       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG007);
-	writel(LN0_OVRD_TX_DRV_PRE_LVL_G1,
-	       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG009);
-	writel(LN0_OVRD_RX_CTLE_RS1_G1,
-	       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG059);
-	writel(LN0_OVRD_RX_CTLE_RS1_G2_G3,
-	       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG060);
-	writel(LN0_ANA_RX_CTLE_IBLEED,
-	       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG069);
-	writel(LN0_OVRD_RX_RTERM_VCM_EN,
-	       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG107);
-	writel(LN0_ANA_OVRD_RX_SQHS_DIFN_OC,
-	       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG109);
-	writel(LN0_ANA_OVRD_RX_SQHS_DIFP_OC,
-	       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG110);
-	writel(LN0_RX_CDR_FBB_FINE_G1_G2,
-	       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG158);
-	writel(LN0_RX_CDR_FBB_FINE_G3_G4,
-	       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG159);
-	writel(LN0_TG_RX_SIGVAL_LBF_DELAY,
-	       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG206);
+	if (imx8_pcie_phy_tuned) {
+		writel(LN0_OVRD_TX_DRV_LVL,
+		       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG001);
+		writel(LN0_OVRD_TX_DRV_PST_LVL_G1,
+		       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG005);
+		writel(LN0_OVRD_TX_DRV_PST_LVL_G2,
+		       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG006);
+		writel(LN0_OVRD_TX_DRV_PST_LVL_G3,
+		       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG007);
+		writel(LN0_OVRD_TX_DRV_PRE_LVL_G1,
+		       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG009);
+		writel(LN0_OVRD_RX_CTLE_RS1_G1,
+		       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG059);
+		writel(LN0_OVRD_RX_CTLE_RS1_G2_G3,
+		       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG060);
+		writel(LN0_ANA_RX_CTLE_IBLEED,
+		       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG069);
+		writel(LN0_OVRD_RX_RTERM_VCM_EN,
+		       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG107);
+		writel(LN0_ANA_OVRD_RX_SQHS_DIFN_OC,
+		       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG109);
+		writel(LN0_ANA_OVRD_RX_SQHS_DIFP_OC,
+		       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG110);
+		writel(LN0_RX_CDR_FBB_FINE_G1_G2,
+		       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG158);
+		writel(LN0_RX_CDR_FBB_FINE_G3_G4,
+		       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG159);
+		writel(LN0_TG_RX_SIGVAL_LBF_DELAY,
+		       imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG206);
+	}
 
 	writel(PLL_ANA_LPF_R_SEL_FINE_0_4,
 	       imx8_phy->base + IMX8MP_PCIE_PHY_CMN_REG020);
@@ -198,6 +201,17 @@ static struct phy_ops imx8_pcie_phy_ops = {
 	.owner		= THIS_MODULE,
 };
 
+static int __init imx8_pcie_phy_fine_tune(char *str)
+{
+	if (!strcmp(str, "yes")) {
+		pr_info("i.MX PCIe PHY is fine tuned in EP/RC SYS.\n");
+		imx8_pcie_phy_tuned = 1;
+	}
+	return 1;
+}
+
+__setup("pcie_phy_tuned=", imx8_pcie_phy_fine_tune);
+
 static int imx8_pcie_phy_probe(struct platform_device *pdev)
 {
 	u32 val = 0;