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Add support for WCH CH56x series SoC #64472

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Add support for WCH CH56x series SoC #64472

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@xingrz xingrz commented Oct 27, 2023 •
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QingKe is a series of RISC-V cores developed by WCH, consisting with V2A, V3A and V4B/C/F series of MCUs.

CH569/CH565 are 2 of the members of the QingKe V3A series. This PR brings initial support for these two SoCs to Zephyr.

In summary, this PR includes:

  • An interrupt controller for all QingKe MCUs.
  • A systick driver for the QingKe V3 series.
  • Clock controller and GPIO, UART driver specifically for the CH56x MCUs.
  • Configurations for the official CH565W-EVT and CH569W-EVT evaluation boards

Support for other series members will be submit in future PRs.

References:

TODOs

@xingrz xingrz force-pushed the wch/pr/ch56x-bringup branch 4 times, most recently from a10ccca to 80ce4f7 Compare October 27, 2023 06:45
@xingrz xingrz marked this pull request as ready for review October 27, 2023 07:31
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xingrz commented May 20, 2024

@xingrz I will output the uart0 of ch592f as the console, with a baud rate of 115200. However, the actual baud rate seen on the oscilloscope is 114khz. I am not sure where the problem is and how to modify it. I look forward to your prompt. Thank you!

Maybe you need to revert the latest [WIP] TICKLESS] commit from that branch.

We're off-topic. You can contact me from the official Discord.

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This pull request has been marked as stale because it has been open (more than) 60 days with no activity. Remove the stale label or add a comment saying that you would like to have the label removed otherwise this pull request will automatically be closed in 14 days. Note, that you can always re-open a closed pull request at any time.

@github-actions github-actions bot added the Stale label Jul 23, 2024
@github-actions github-actions bot closed this Aug 7, 2024
@xingrz xingrz mentioned this pull request Sep 4, 2024
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@xingrz xingrz reopened this Sep 4, 2024
@xingrz xingrz force-pushed the wch/pr/ch56x-bringup branch 2 times, most recently from cc6495c to e6ed4e0 Compare September 4, 2024 14:58
@xingrz
[DNM] arch: riscv: Add support for custom interrupt controller
afd3b7c 
NOTE: Duplicated with an existing PR. Leaving this commit here just as
a placeholder. Will be rebased soon after that existing PR get merged.

==========================================================================

In certain cases, platforms may have their own implemented interrupt
controllers (e.g., the PFIC on WCH MCUs) that require the ability to
implement the irq_enable/disable functions at the SoC level.

Similar support already exists for ARM and ARM64. This commit adds support
for RISC-V as well.

Signed-off-by: Chen Xingyu <[email protected]>

# Conflicts:
#	include/zephyr/arch/riscv/irq.h
@xingrz
dts/soc: wch: Add WCH QingKe V3 series
0cd60e9 
QingKe V3 is an RV32IMAC core developed by WCH

Signed-off-by: Chen Xingyu <[email protected]>
@xingrz
dts/soc: wch: ch56x: Add WCH CH569/5 SoC
a05583a 
Based on QingKe V3A core, CH569/5 are members of the CH56x series.

Signed-off-by: Chen Xingyu <[email protected]>
@xingrz
drivers: intc: Implement interrupt controller for WCH QingKe CPUs
6292691 
PFIC (Programmable Fast Interrupt Controller) is the interrupt controller
implmentation in WCH QingKe series RISC-V MCUs.

Signed-off-by: Chen Xingyu <[email protected]>

# Conflicts:
#	drivers/interrupt_controller/CMakeLists.txt
#	drivers/interrupt_controller/Kconfig
@xingrz
drivers: timer: Add systick driver for WCH QingKe V3 CPUs
129a608 
This driver is shared across QingKe V3A series, including CH32V103,
CH569/5 and CH573/1.

Signed-off-by: Chen Xingyu <[email protected]>
@xingrz
dts/soc: wch: ch56x: Add syscon node for WCH CH56x
bcc5ea7 
This commit describes the system control block of the CH56x in DTS. This
block will be utilized in future drivers for functions such as pin
remapping, clock control, and interrupt management.

Additionally, macros has been added to facilitate easy access to the block.

Signed-off-by: Chen Xingyu <[email protected]>
@xingrz
drivers: clock: Implement system clock mux controller for CH56x
2d4afeb 
The CH56x can be configured to run on a 30MHz external oscillator or a
480MHz PLL generated by the USB PHY.

This commit introduces a clock controller that can automatically select
one of the two available clock sources and determine the appropriate
divisor based on the given frequency.

The `CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC` value is also updated with the
selected frequency.

Signed-off-by: Chen Xingyu <[email protected]>

# Conflicts:
#	drivers/clock_control/Kconfig
#	soc/riscv/riscv-privileged/wch_ch32v/Kconfig.defconfig.ch56x
@xingrz
drivers: gpio: Add GPIO driver for WCH CH56x
67d516c 
This commit implements a GPIO driver for CH56x series.

The 2 instances of GPIO share a same IRQ line on this chip. So the config
`SHARED_IRQ` is selected as well.

Signed-off-by: Chen Xingyu <[email protected]>
@xingrz
drivers: pinctrl: Implement pin controller for WCH CH5xx series
4d436d3 
This commit introduces a pinctrl driver for the CH5xx series.

The limitations of pin multiplexing of WCH CH5xx series are described
in the binding configuration.

Signed-off-by: Chen Xingyu <[email protected]>
@xingrz
drivers: serial: Implement UART driver for WCH CH5xx series
128f202 
This commit introduces UART driver for CH5xx series, supporting both
polling and interrupt-driven mode.

Signed-off-by: Chen Xingyu <[email protected]>
@xingrz
scripts: runners: Add wrapper for WCHISPTool
4ad9fd3 
`WCHISPTool_CMD` is the commandline version of WCHISPTool, which is a USB
flashing tool for WCH series MCUs.

Signed-off-by: Chen Xingyu <[email protected]>
@xingrz
boards: wch: Bring up WCH CH56(5/9)W-EVT
d3c4086 
CH565W-EVT and CH569W-EVT are boards by WCH for the evaluation of
CH565W and CH569W chips.

Signed-off-by: Chen Xingyu <[email protected]>
@xingrz
MAINTAINERS: Add WCH platform and assign myself as maintainer
7cd499e 
* Add `WCH Platforms` section
* Add `xingrz` to maintainers of `WCH Platform`

Signed-off-by: Chen Xingyu <[email protected]>
@github-actions github-actions bot removed the Stale label Sep 5, 2024
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goutnet commented Oct 15, 2024

I am very interested to follow this PR, how can I help @xingrz

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soburi commented Oct 15, 2024

@xingrz

#66505 seems like a long-term task to finish.
I propose this PR progressing with the current ISR implementation.
What do you think?

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Labels
area: Architectures area: Clock Control area: Devicetree Binding PR modifies or adds a Device Tree binding area: GPIO area: Interrupt Controller area: Process area: RISCV RISCV Architecture (32-bit & 64-bit) area: Timer Timer area: West West utility
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