-
Notifications
You must be signed in to change notification settings - Fork 6.6k
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Support edma3 for s32z270dc2 board #78368
Support edma3 for s32z270dc2 board #78368
Conversation
The following west manifest projects have been modified in this Pull Request:
Note: This message is automatically posted and updated by the Manifest GitHub Action. |
tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay
Outdated
Show resolved
Hide resolved
tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay
Outdated
Show resolved
Hide resolved
6d05b95
to
8efc8f3
Compare
Added commit to Split |
@teburd @manuargue @Dat-NguyenDuy please help me take a look into this PR. All comments addressed. Thanks |
Hi @teburd, Could you please help me take a look into this PR? |
a47d71e
262db2c
to
a47d71e
Compare
I rebased and fixed the conflict. |
@teburd I've add @manuargue (NXP S32 platform maintainer) as a co-assignee so we can move forward with this PR. |
@haduongquang HAL pr merged, please rebase and update manifest to 4597b16cfedf5553cb155151e65eb994d5d0ef25 |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
blocking until #78314 is merged and update the manifest
Support multiple instances for dma. Memset struct data and tcdpool on initialization is not necessary. Therefore remove it. Signed-off-by: Ha Duong Quang <[email protected]>
9158449
a47d71e
to
9158449
Compare
I rebased and updated the manifest |
Enable support EDMA for S32Z270. Add eDMA3 instance 0, 1, 4 and 5 for S32Z270 devices. Signed-off-by: Ha Duong Quang <[email protected]>
Enable dma boards/test for S32Z270. The non-cacheable memory used for DMA tests (chan_blen_transfer and loop_transfer) is split from the system SRAM. Signed-off-by: Ha Duong Quang <[email protected]>
9158449
to
aeb0801
Compare
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
dismiss #78368 (review), my mistake, first we need to merge this pr
This PR introduces NXP S32 EDMA3 driver for SoC NXP S32Z27 and enables its usage for board s32z270dc2
Tests:
tests\drivers\dma\chan_blen_transfer:
SUITE PASS - 100.00% [dma_m2m]: pass = 4, fail = 0, skip = 0, total = 4 duration = 8.063 seconds
tests\drivers\dma\chan_link_transfer:
SUITE PASS - 100.00% [dma_m2m_link]: pass = 3, fail = 0, skip = 0, total = 3 duration = 6.047 seconds
tests\drivers\dma\loop_transfer:
SUITE PASS - 100.00% [dma_m2m_loop]: pass = 3, fail = 0, skip = 0, total = 3 duration = 1.103 seconds
tests\drivers\dma\scatter_gather:
SUITE PASS - 100.00% [dma_m2m_sg]: pass = 1, fail = 0, skip = 0, total = 1 duration = 0.076 seconds