Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Add STM32WLE5 for custom targets LORA_E5 and RAK3172 #14872

Merged
merged 8 commits into from
Jul 8, 2021
Merged

Add STM32WLE5 for custom targets LORA_E5 and RAK3172 #14872

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
8 commits
Select commit Hold shift + click to select a range
cf7e1eb
moved to STM32WL up folder
hallard Jul 5, 2021
d601dd8
moved to STM32WL up folder
hallard Jul 5, 2021
38eed85
moved system_clock.c to STM32WL up folder
hallard Jul 5, 2021
37814f2
added target stm32wle5xc
hallard Jul 5, 2021
ca32375
added STM32WLE5JCIx
hallard Jul 5, 2021
51cfdc2
moved to up folder common to STM32WL
hallard Jul 5, 2021
e598f5f
typo + moved device_name
hallard Jul 6, 2021
c8fdc0a
added STM32WLE5CCUx + version 1.1.0
hallard Jul 6, 2021
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@ target_sources(mbed-stm32wl
pwmout_device.c
serial_device.c
spi_api.c
system_clock.c
)

target_include_directories(mbed-stm32wl
Expand Down
0 ...xC/TARGET_NUCLEO_WL55JC/PeripheralNames.h → ...RGET_STM/TARGET_STM32WL/PeripheralNames.h
View file
Open in desktop
File renamed without changes.
1 change: 0 additions & 1 deletion targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@ add_library(mbed-nucleo-wl55jc INTERFACE)
target_sources(mbed-nucleo-wl55jc
INTERFACE
PeripheralPins.c
system_clock.c
)

target_include_directories(mbed-nucleo-wl55jc
Expand Down
26 changes: 26 additions & 0 deletions targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,26 @@
# Copyright (c) 2020 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0

if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S)
set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wle5xc.ld)
elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32wle5xx.S)
set(LINKER_FILE TOOLCHAIN_ARM/stm32wle5xc.sct)
endif()

add_library(mbed-stm32wle5xc INTERFACE)

target_sources(mbed-stm32wle5xc
INTERFACE
${STARTUP_FILE}
)

target_include_directories(mbed-stm32wle5xc
INTERFACE
.
)

mbed_set_linker_script(mbed-stm32wle5xc ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})

target_link_libraries(mbed-stm32wle5xc INTERFACE mbed-stm32wl)
0 ...L55xC/TARGET_NUCLEO_WL55JC/system_clock.c → .../TARGET_STM/TARGET_STM32WL/system_clock.c
View file
Open in desktop
File renamed without changes.
16 changes: 16 additions & 0 deletions targets/targets.json
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4381,6 +4381,22 @@
],
"device_name": "STM32WL55JCIx"
},
"MCU_STM32WLE5xC": {
"inherits": [
"MCU_STM32WL"
],
"public": false,
"macros_add": [
"STM32WLE5xx"
],
"extra_labels_add": [
"STM32WLE5xC"
],
"mbed_rom_start": "0x8000000",
"mbed_rom_size": "0x40000",
"mbed_ram_start": "0x20000000",
"mbed_ram_size": "0x10000"
},
"MIMXRT1050_EVK": {
"supported_form_factors": [
"ARDUINO_UNO"
Expand Down
136 changes: 136 additions & 0 deletions tools/arm_pack_manager/index.json
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -480222,6 +480222,142 @@
]
],
"sub_family": "STM32WL55"
},
"STM32WLE5JCIx": {
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Maybe adding also STM32WLE5CCUx for RAK3172 could be a good idea ?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

of course, that's done

"name": "STM32WLE5JCIx:CM4",
"memories": {
"IRAM1": {
"access": {
"read": true,
"write": true,
"execute": false,
"peripheral": false,
"secure": false,
"non_secure": false,
"non_secure_callable": false
},
"start": 536870912,
"size": 65536,
"startup": false,
"default": true
},
"IROM1": {
"access": {
"read": true,
"write": false,
"execute": true,
"peripheral": false,
"secure": false,
"non_secure": false,
"non_secure_callable": false
},
"start": 134217728,
"size": 262144,
"startup": true,
"default": true
}
},
"algorithms": [
{
"file_name": "CMSIS/Flash/STM32WLxx_CM4.FLM",
"start": 134217728,
"size": 262144,
"default": true,
"ram_start": null,
"ram_size": null
}
],
"processor": {
"Symmetric": {
"units": 1,
"core": "CortexM4",
"fpu": "None",
"mpu": "Present"
}
},
"from_pack": {
"vendor": "Keil",
"pack": "STM32WLxx_DFP",
"version": "1.1.0",
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

1.1.0 ?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

correct, it's fixed, may be should be also done for WL55 (nucleo)?

Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

not mandatory, as MCU from NUCLEO was already available in 1.0.0, I think

"url": "http://www.keil.com/pack"
},
"vendor": "STMicroelectronics:13",
"family": "STM32WL Series",
"sectors": [
[
134217728,
2048
]
],
"sub_family": "STM32WLE5"
},
"STM32WLE5CCUx": {
"name": "STM32WLE5CCUx:CM4",
"memories": {
"IRAM1": {
"access": {
"read": true,
"write": true,
"execute": false,
"peripheral": false,
"secure": false,
"non_secure": false,
"non_secure_callable": false
},
"start": 536870912,
"size": 65536,
"startup": false,
"default": true
},
"IROM1": {
"access": {
"read": true,
"write": false,
"execute": true,
"peripheral": false,
"secure": false,
"non_secure": false,
"non_secure_callable": false
},
"start": 134217728,
"size": 262144,
"startup": true,
"default": true
}
},
"algorithms": [
{
"file_name": "CMSIS/Flash/STM32WLxx_CM4.FLM",
"start": 134217728,
"size": 262144,
"default": true,
"ram_start": null,
"ram_size": null
}
],
"processor": {
"Symmetric": {
"units": 1,
"core": "CortexM4",
"fpu": "None",
"mpu": "Present"
}
},
"from_pack": {
"vendor": "Keil",
"pack": "STM32WLxx_DFP",
"version": "1.1.0",
"url": "http://www.keil.com/pack"
},
"vendor": "STMicroelectronics:13",
"family": "STM32WL Series",
"sectors": [
[
134217728,
2048
]
],
"sub_family": "STM32WLE5"
},
"STM32WB15CCUx": {
"name": "STM32WB15CCUx",
Expand Down