Merge pull request #195 from coreboot/main

[pull] main from coreboot:main

src/mainboard/google/rauru/Kconfig

@@ -2,7 +2,8 @@
 
 # Umbrella option to be selected by variant boards.
 config BOARD_GOOGLE_RAURU_COMMON
-	def_bool BOARD_GOOGLE_RAURU
+	def_bool BOARD_GOOGLE_NAVI || \
+		 BOARD_GOOGLE_RAURU
 
 if BOARD_GOOGLE_RAURU_COMMON
 
@@ -26,6 +27,7 @@ config MAINBOARD_DIR
 
 config MAINBOARD_PART_NUMBER
 	string
+	default "Navi" if BOARD_GOOGLE_NAVI
 	default "Rauru" if BOARD_GOOGLE_RAURU
 
 config BOOT_DEVICE_SPI_FLASH_BUS

src/mainboard/google/rauru/Kconfig.name

@@ -4,3 +4,6 @@ comment "Rauru"
 
 config BOARD_GOOGLE_RAURU
 	bool "->  Rauru"
+
+config BOARD_GOOGLE_NAVI
+	bool "->  Navi"

src/mainboard/google/rauru/bootblock.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootblock_common.h>
+#include <gpio.h>
 #include <soc/spi.h>
 
 #include "gpio.h"
@@ -14,4 +15,5 @@ void bootblock_mainboard_init(void)
 {
 	mtk_snfc_init();
 	usb3_hub_reset();
+	setup_chromeos_gpios();
 }

src/mainboard/google/rauru/chromeos.c

@@ -1,8 +1,26 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <boot/coreboot_tables.h>
+#include <gpio.h>
+
+#include "gpio.h"
+
+void setup_chromeos_gpios(void)
+{
+	gpio_output(GPIO_AP_FP_FW_UP_STRAP, 0);
+	gpio_output(GPIO_BEEP_ON_OD, 0);
+	gpio_output(GPIO_EN_PWR_FP, 0);
+	gpio_output(GPIO_EN_SPKR, 0);
+	gpio_output(GPIO_FP_RST_1V8_S3_L, 0);
+	gpio_output(GPIO_XHCI_INIT_DONE, 0);
+}
 
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
-	/* TODO: add ChromeOS specific gpios */
+	struct lb_gpio chromeos_gpios[] = {
+		{ GPIO_XHCI_INIT_DONE.id, ACTIVE_HIGH, -1, "XHCI init done" },
+		{ GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable" },
+		{ GPIO_BEEP_ON_OD.id, ACTIVE_HIGH, -1, "beep enable" },
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }

src/mainboard/google/rauru/gpio.h

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MAINBOARD_GOOGLE_RAURU_GPIO_H__
+#define __MAINBOARD_GOOGLE_RAURU_GPIO_H__
+
+#include <soc/gpio.h>
+
+#define GPIO_BEEP_ON_OD		GPIO(PERIPHERAL_EN1)
+#define GPIO_EN_SPKR		GPIO(PERIPHERAL_EN0)
+#define GPIO_XHCI_INIT_DONE	GPIO(EINT28)
+#define GPIO_FP_RST_1V8_S3_L	GPIO(EINT26)
+#define GPIO_AP_FP_FW_UP_STRAP	GPIO(EINT27)
+#define GPIO_EN_PWR_FP		GPIO(PERIPHERAL_EN3)
+
+void setup_chromeos_gpios(void);
+
+#endif

src/mainboard/google/rauru/mainboard.c

@@ -1,11 +1,22 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/device.h>
+#include <gpio.h>
 #include <soc/usb.h>
 
+#include "gpio.h"
+
+static void power_on_fpmcu(void)
+{
+	/* Power on the fingerprint MCU */
+	gpio_output(GPIO_EN_PWR_FP, 1);
+	gpio_output(GPIO_FP_RST_1V8_S3_L, 1);
+}
+
 static void mainboard_init(struct device *dev)
 {
 	setup_usb_host();
+	power_on_fpmcu();
 }
 
 static void mainboard_enable(struct device *dev)

src/soc/intel/xeon_sp/Makefile.mk

@@ -5,8 +5,7 @@ ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y)
 subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx lbg
 subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx lbg
 subdirs-$(CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP) += spr ebg
-## TODO: GNR IBL codes are initially reused from EBG, will update later.
-subdirs-$(CONFIG_SOC_INTEL_GRANITERAPIDS) += gnr ebg
+subdirs-$(CONFIG_SOC_INTEL_GRANITERAPIDS) += gnr ibl
 
 bootblock-y += bootblock.c spi.c lpc.c pch.c report_platform.c
 romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c ddr.c

src/soc/intel/xeon_sp/ibl/Makefile.mk

@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += soc_gpio.c soc_pch.c
+romstage-y += soc_gpio.c soc_pmutil.c soc_pch.c
+ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c
+
+CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/ibl/include

src/soc/intel/xeon_sp/ibl/include/soc/azalia_device.h

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DEVICE_AZALIA_H
+#define DEVICE_AZALIA_H
+
+#define HDA_PCS			0x54
+#define  HDA_PCS_PS_D3HOT	3
+
+#endif /* DEVICE_AZALIA_H */