Merge pull request #176 from coreboot/main

[pull] main from coreboot:main

src/mainboard/51nb/x210/devicetree.cb

@@ -39,29 +39,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpSusMinAssert" = "3"	# 500ms
 	register "PmConfigSlpAMinAssert" = "3"		# 2s
 
-	# Enable Root Ports 3, 4 and 9
-	register "PcieRpEnable[2]" = "1" # Ethernet controller
-	register "PcieRpClkReqSupport[2]" = "1"
-	register "PcieRpClkReqNumber[2]" = "0"
-	register "PcieRpClkSrcNumber[2]" = "0"
-	register "PcieRpAdvancedErrorReporting[2]" = "1"
-	register "PcieRpLtrEnable[2]" = "1"
-
-	register "PcieRpEnable[3]" = "1" # Wireless controller
-	register "PcieRpClkReqSupport[3]" = "1"
-	register "PcieRpClkReqNumber[3]" = "1"
-	register "PcieRpClkSrcNumber[3]" = "1"
-	register "PcieRpAdvancedErrorReporting[3]" = "1"
-	register "PcieRpLtrEnable[3]" = "1"
-
-	register "PcieRpEnable[8]" = "1" # NVMe controller
-	register "PcieRpClkReqSupport[8]" = "1"
-	register "PcieRpClkReqNumber[8]" = "4"
-	register "PcieRpClkSrcNumber[8]" = "4"
-	register "PcieRpAdvancedErrorReporting[8]" = "1"
-	register "PcieRpLtrEnable[8]" = "1"
-
-
 	# PL1 override 25W
 	# PL2 override 44W
 	register "power_limits_config" = "{
@@ -110,9 +87,33 @@ chip soc/intel/skylake
 				[2] = 1,
 			}"
 		end
-		device ref pcie_rp3	on  end
-		device ref pcie_rp4	on  end
-		device ref pcie_rp9	on  end
+		device ref pcie_rp3	on
+			# Ethernet controller
+			register "PcieRpEnable[2]" = "1"
+			register "PcieRpClkReqSupport[2]" = "1"
+			register "PcieRpClkReqNumber[2]" = "0"
+			register "PcieRpClkSrcNumber[2]" = "0"
+			register "PcieRpAdvancedErrorReporting[2]" = "1"
+			register "PcieRpLtrEnable[2]" = "1"
+		end
+		device ref pcie_rp4	on
+			# Wireless controller
+			register "PcieRpEnable[3]" = "1"
+			register "PcieRpClkReqSupport[3]" = "1"
+			register "PcieRpClkReqNumber[3]" = "1"
+			register "PcieRpClkSrcNumber[3]" = "1"
+			register "PcieRpAdvancedErrorReporting[3]" = "1"
+			register "PcieRpLtrEnable[3]" = "1"
+		end
+		device ref pcie_rp9	on
+			# NVMe controller
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqNumber[8]" = "4"
+			register "PcieRpClkSrcNumber[8]" = "4"
+			register "PcieRpAdvancedErrorReporting[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+		end
 		device ref lpc_espi	on
 			register "serirq_mode" = "SERIRQ_CONTINUOUS"
 

src/mainboard/facebook/monolith/devicetree.cb

@@ -111,57 +111,6 @@ chip soc/intel/skylake
 	# Send an extra VR mailbox command for the PS4 exit issue
 	register "SendVrMbxCmd" = "2"
 
-	# Enable Root ports.
-	# PCIE Port 1 disabled
-	# PCIE Port 2 disabled
-
-	# PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard
-	register "PcieRpEnable[2]" = "1"
-	# Disable CLKREQ#
-	register "PcieRpClkReqSupport[2]" = "0"
-	# Set MaxPayload to 256 bytes
-	register "PcieRpMaxPayload[2]" = "RpMaxPayload_256"
-	# Enable Latency Tolerance Reporting Mechanism
-	register "PcieRpLtrEnable[2]" = "1"
-	# Enable Advanced Error Reporting
-	register "PcieRpAdvancedErrorReporting[2]" = "1"
-	# Disable Aspm
-	register "pcie_rp_aspm[2]" = "AspmDisabled"
-
-	# PCIE Port 4 disabled
-	# PCIE Port 5 x1 -> MODULE i219
-
-	# PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard
-	register "PcieRpEnable[5]" = "1"
-	register "PcieRpClkReqSupport[5]" = "0"
-	# Set MaxPayload to 256 bytes
-	register "PcieRpMaxPayload[5]" = "RpMaxPayload_256"
-	# Enable Latency Tolerance Reporting Mechanism
-	register "PcieRpLtrEnable[5]" = "1"
-	# Enable Advanced Error Reporting
-	register "PcieRpAdvancedErrorReporting[5]" = "1"
-	# Disable Aspm
-	register "pcie_rp_aspm[5]" = "AspmDisabled"
-
-	# PCIE Port 7 Disabled
-	# PCIE Port 8 Disabled
-
-	# PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA
-	register "PcieRpEnable[8]" = "1"
-	# Disable CLKREQ#
-	register "PcieRpClkReqSupport[8]" = "0"
-	# Use Hot Plug subsystem
-	register "PcieRpHotPlug[8]" = "1"
-	# Set MaxPayload to 256 bytes
-	register "PcieRpMaxPayload[8]" = "RpMaxPayload_256"
-	# Enable Latency Tolerance Reporting Mechanism
-	register "PcieRpLtrEnable[8]" = "1"
-	# Enable Advanced Error Reporting
-	register "PcieRpAdvancedErrorReporting[8]" = "1"
-	# Disable Aspm
-	register "pcie_rp_aspm[8]" = "AspmDisabled"
-
-
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
 	register "SerialIoDevMode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoDisabled,
@@ -205,9 +154,37 @@ chip soc/intel/skylake
 			register "SataSalpSupport" = "1"
 			register "SataPortsEnable[0]" = "1"
 		end
-		device ref pcie_rp3	on  end # x1 baseboard WWAN
-		device ref pcie_rp6	on  end # x1 baseboard i210
-		device ref pcie_rp9	on  end # x4 FPGA
+		device ref pcie_rp3	on
+			# x1 baseboard WWAN
+			# PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard
+			register "PcieRpEnable[2]" = "1"
+			register "PcieRpClkReqSupport[2]" = "0"
+			register "PcieRpMaxPayload[2]" = "RpMaxPayload_256"
+			register "PcieRpLtrEnable[2]" = "1"
+			register "PcieRpAdvancedErrorReporting[2]" = "1"
+			register "pcie_rp_aspm[2]" = "AspmDisabled"
+		end
+		device ref pcie_rp6	on
+			# x1 baseboard i210
+			# PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard
+			register "PcieRpEnable[5]" = "1"
+			register "PcieRpClkReqSupport[5]" = "0"
+			register "PcieRpMaxPayload[5]" = "RpMaxPayload_256"
+			register "PcieRpLtrEnable[5]" = "1"
+			register "PcieRpAdvancedErrorReporting[5]" = "1"
+			register "pcie_rp_aspm[5]" = "AspmDisabled"
+		end
+		device ref pcie_rp9	on
+			# x4 FPGA
+			# PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "0"
+			register "PcieRpHotPlug[8]" = "1"
+			register "PcieRpMaxPayload[8]" = "RpMaxPayload_256"
+			register "PcieRpLtrEnable[8]" = "1"
+			register "PcieRpAdvancedErrorReporting[8]" = "1"
+			register "pcie_rp_aspm[8]" = "AspmDisabled"
+		end
 		device ref uart0	on  end
 		device ref emmc		on  end
 		device ref lpc_espi	on

src/mainboard/google/brox/variants/lotso/overridetree.cb

@@ -6,26 +6,30 @@ fw_config
 	end
 	field STORAGE 2 3
 		option STORAGE_UNKNOWN		0
-		option STORAGE_UFS			1
-		option STORAGE_NVME			2
+		option STORAGE_UFS		1
+		option STORAGE_NVME		2
 	end
 	field WIFI_BT 4 4
 		option WIFI_CNVI_WIFI6E		0
 		option WIFI_PCIE_WIFI7		1
 	end
 	field AUDIO 5 7
 		option AUDIO_UNKNOWN		0
-		option AUDIO_REALTEK_ALC256		1
+		option AUDIO_REALTEK_ALC256	1
 		option AUDIO_REALTEK_ALC3287	2
 	end
 	field UFC 8 9
-		option UFC_NONE		0
-		option UFC_USB		1
+		option UFC_NONE			0
+		option UFC_USB			1
 	end
 	field KB_BL 10 10
-		option KB_BL_ABSENT			0
+		option KB_BL_ABSENT		0
 		option KB_BL_PRESENT		1
 	end
+	field FP 11 12
+		option FP_PRESENT		0
+		option FP_ABSENT		1
+	end
 	field ISH 21
 		option ISH_DISABLE		0
 		option ISH_ENABLE		1

src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb

@@ -11,6 +11,7 @@ fw_config
 		option STORAGE_EMMC		0
 		option STORAGE_NVME		1
 		option STORAGE_UFS		2
+		option STORAGE_UNKNOWN		3
 	end
 end
 

src/mainboard/google/brya/variants/bujia/overridetree.cb

@@ -151,16 +151,11 @@ chip soc/intel/alderlake
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 		end #NVME
+		device ref tbt_pcie_rp0 off end
 		device ref tbt_pcie_rp1 off end
 		device ref tbt_pcie_rp2 off end
 
-		device ref tcss_dma0 on
-			chip drivers/intel/usb4/retimer
-				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
-				use tcss_usb3_port1 as dfp[0].typec_port
-				device generic 0 on end
-			end
-		end
+		device ref tcss_dma0 off end
 		device ref tcss_dma1 off end
 		device ref cnvi_wifi on
 			chip drivers/wifi/generic

src/mainboard/google/brya/variants/riven/Makefile.mk

@@ -4,5 +4,4 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
-ramstage-$(CONFIG_FW_CONFIG) += variant.c
 ramstage-y += gpio.c

src/mainboard/google/brya/variants/riven/fw_config.c

@@ -90,9 +90,11 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 						ARRAY_SIZE(stylus_disable_pads));
 	}
 
-	if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) {
-		printk(BIOS_INFO, "Disable eMMC GPIO pins.\n");
-		gpio_padbased_override(padbased_table, emmc_disable_pads,
+	if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
+		if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) {
+			printk(BIOS_INFO, "Disable eMMC GPIO pins.\n");
+			gpio_padbased_override(padbased_table, emmc_disable_pads,
 						ARRAY_SIZE(emmc_disable_pads));
+		}
 	}
 }

src/mainboard/google/brya/variants/riven/overridetree.cb

@@ -478,14 +478,22 @@ chip soc/intel/alderlake
 			end
 		end
 		device ref pcie_rp7 off end # PCIE7 no SD card
-		device ref emmc on end
+		device ref emmc on
+			probe STORAGE STORAGE_UNKNOWN
+			probe STORAGE STORAGE_EMMC
+		end
 		device ref ish on
 			chip drivers/intel/ish
 				register "add_acpi_dma_property" = "true"
 				device generic 0 on end
 			end
+			probe STORAGE STORAGE_UNKNOWN
+			probe STORAGE STORAGE_UFS
+		end
+		device ref ufs on
+			probe STORAGE STORAGE_UNKNOWN
+			probe STORAGE STORAGE_UFS
 		end
-		device ref ufs on end
 		device ref pch_espi on
 			chip ec/google/chromeec
 				use conn0 as mux_conn[0]

src/mainboard/google/eve/devicetree.cb

@@ -116,25 +116,6 @@ chip soc/intel/skylake
 		.dc_loadline = 430,
 	}"
 
-	# Enable Root port 1 with SRCCLKREQ1#
-	register "PcieRpEnable[0]" = "1"
-	register "PcieRpClkReqSupport[0]" = "1"
-	register "PcieRpClkReqNumber[0]" = "1"
-	register "PcieRpAdvancedErrorReporting[0]" = "1"
-	register "PcieRpLtrEnable[0]" = "1"
-	register "PcieRpHotPlug[0]" = "1"
-	#RP 1 uses CLK SRC 1
-	register "PcieRpClkSrcNumber[0]" = "1"
-
-	# Enable Root port 5 with SRCCLKREQ4#
-	register "PcieRpEnable[4]" = "1"
-	register "PcieRpClkReqSupport[4]" = "1"
-	register "PcieRpClkReqNumber[4]" = "4"
-	register "PcieRpAdvancedErrorReporting[4]" = "1"
-	register "PcieRpLtrEnable[4]" = "1"
-	#RP 5 uses CLK SRC 4
-	register "PcieRpClkSrcNumber[4]" = "4"
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -355,12 +336,26 @@ chip soc/intel/skylake
 			end
 		end # I2C #4
 		device ref pcie_rp1	on
+			register "PcieRpEnable[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqNumber[0]" = "1"
+			register "PcieRpAdvancedErrorReporting[0]" = "1"
+			register "PcieRpLtrEnable[0]" = "1"
+			register "PcieRpHotPlug[0]" = "1"
+			register "PcieRpClkSrcNumber[0]" = "1"
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PCI_EXP"
 				device pci 00.0 on end
 			end
 		end
-		device ref pcie_rp5	on  end
+		device ref pcie_rp5	on
+			register "PcieRpEnable[4]" = "1"
+			register "PcieRpClkReqSupport[4]" = "1"
+			register "PcieRpClkReqNumber[4]" = "4"
+			register "PcieRpAdvancedErrorReporting[4]" = "1"
+			register "PcieRpLtrEnable[4]" = "1"
+			register "PcieRpClkSrcNumber[4]" = "4"
+		end
 		device ref uart0	on  end
 		device ref gspi0	on
 			chip drivers/spi/acpi