i#3544 RV64: Added an encoder and some fixes and improvments to the decoder

.github/workflows/ci-riscv64.yml

@@ -94,6 +94,7 @@ jobs:
         DYNAMORIO_CROSS_RISCV64_LINUX_ONLY: yes
         CI_TRIGGER: ${{ github.event_name }}
         CI_BRANCH: ${{ github.ref }}
+        QEMU_LD_PREFIX: /usr/riscv64-linux-gnu/
 
     - name: Send failure mail to dynamorio-devs
       if: failure() && github.ref == 'refs/heads/master'

clients/drdisas/drdisas.cpp

@@ -67,7 +67,7 @@ droption_t<bool> op_show_bytes(DROPTION_SCOPE_FRONTEND, "show_bytes", true,
                                "Display the instruction encoding bytes.",
                                "Display the instruction encoding bytes.");
 
-#if defined(AARCH64) || defined(ARM)
+#if defined(AARCH64) || defined(ARM) || defined(RISCV64)
 #    define MAX_INSTR_LENGTH 4
 #else
 #    define MAX_INSTR_LENGTH 17

core/drlibc/drlibc_module_elf.c

@@ -130,7 +130,8 @@ is_elf_so_header_common(app_pc base, size_t size, bool memory)
         ASSERT_CURIOSITY(!memory ||
 #ifdef X64
                          elf_header.e_machine == EM_X86_64 ||
-                         elf_header.e_machine == EM_AARCH64
+                         elf_header.e_machine == EM_AARCH64 ||
+                         elf_header.e_machine == EM_RISCV
 #else
                          elf_header.e_machine == EM_386 || elf_header.e_machine == EM_ARM
 #endif

core/ir/disassemble_shared.c

@@ -399,6 +399,11 @@ opnd_base_disp_disassemble(char *buf, size_t bufsz, size_t *sofar INOUT, opnd_t
                 print_to_buffer(buf, bufsz, sofar, "-");
             }
         }
+#if defined(RISCV64)
+        const char *fmt =
+            TEST(opnd_get_flags(opnd), DR_OPND_IMM_PRINT_DECIMAL) ? "%d" : "0x%x";
+        print_to_buffer(buf, bufsz, sofar, fmt, disp);
+#else
         if (TEST(DR_DISASM_ARM, DYNAMO_OPTION(disasm_mask)))
             print_to_buffer(buf, bufsz, sofar, "%d", disp);
         else if ((unsigned)disp <= 0xff && !opnd_is_disp_force_full(opnd))
@@ -407,6 +412,7 @@ opnd_base_disp_disassemble(char *buf, size_t bufsz, size_t *sofar INOUT, opnd_t
             print_to_buffer(buf, bufsz, sofar, "0x%04x", disp);
         else /* there are no 64-bit displacements */
             print_to_buffer(buf, bufsz, sofar, "0x%08x", disp);
+#endif
     }
 
     if (!TESTANY(DR_DISASM_INTEL | DR_DISASM_ARM, DYNAMO_OPTION(disasm_mask))) {

core/ir/encode_shared.c

@@ -69,7 +69,7 @@ instr_encode_arch(dcontext_t *dcontext, instr_t *instr, byte *copy_pc, byte *fin
                   bool *has_instr_opnds /*OUT OPTIONAL*/
                       _IF_DEBUG(bool assert_reachable));
 
-#ifdef AARCH64
+#if defined(AARCH64) || defined(RISCV64)
 /* exported
  */
 bool

core/ir/instr_inline_api.h

@@ -343,12 +343,12 @@ opnd_create_pc(app_pc pc)
              .value.reg_and_element_size.reg)
 #    define opnd_get_reg OPND_GET_REG
 
-#    if defined(X86) || defined(RISCV64)
+#    if defined(X86)
 #        define OPND_GET_FLAGS(opnd)                                                     \
             (CLIENT_ASSERT_(                                                             \
                 opnd_is_reg(opnd) || opnd_is_base_disp(opnd) || opnd_is_immed_int(opnd), \
                 "opnd_get_flags called on non-reg non-base-disp non-immed-int opnd") 0)
-#    elif defined(AARCHXX)
+#    elif defined(AARCHXX) || defined(RISCV64)
 #        define OPND_GET_FLAGS(opnd)                                                   \
             (CLIENT_ASSERT_(                                                           \
                  opnd_is_reg(opnd) || opnd_is_base_disp(opnd) ||                       \

core/ir/opnd_api.h

@@ -1174,7 +1174,6 @@ enum {
     DR_REG_X29,     /**< The x29(t4) register. */
     DR_REG_X30,     /**< The x30(t5) register. */
     DR_REG_X31,     /**< The x31(t6) register. */
-    DR_REG_PC,      /**< The program counter. */
     /* GPR aliases */
     DR_REG_ZERO = DR_REG_X0, /**< The hard-wired zero (x0) register. */
     DR_REG_RA = DR_REG_X1,   /**< The return address (x1) register. */
@@ -1209,6 +1208,7 @@ enum {
     DR_REG_T4 = DR_REG_X29,  /**< The 5th temporary (x29) register. */
     DR_REG_T5 = DR_REG_X30,  /**< The 6th temporary (x30) register. */
     DR_REG_T6 = DR_REG_X31,  /**< The 7th temporary (x31) register. */
+    DR_REG_PC,               /**< The program counter. */
     /* Floating point registers */
     DR_REG_F0,   /**< The f0(ft0) floating-point register. */
     DR_REG_F1,   /**< The f1(ft1) floating-point register. */
@@ -1284,10 +1284,10 @@ enum {
     DR_REG_LAST_VALID_ENUM = DR_REG_FCSR, /**< Last valid register enum. */
     DR_REG_LAST_ENUM = DR_REG_FCSR,       /**< Last value of register enums. */
 
-    DR_REG_START_64 = DR_REG_X0,  /**< Start of 64-bit general register enum values. */
-    DR_REG_STOP_64 = DR_REG_X31,  /**< End of 64-bit general register enum values. */
-    DR_REG_START_32 = DR_REG_X0,  /**< Start of 32-bit general register enum values. */
-    DR_REG_STOP_32 = DR_REG_X31,  /**< End of 32-bit general register enum values. */
+    DR_REG_START_64 = DR_REG_X0,  /**< Start of 64-bit register enum values. */
+    DR_REG_STOP_64 = DR_REG_F31,  /**< End of 64-bit register enum values. */
+    DR_REG_START_32 = DR_REG_X0,  /**< Start of 32-bit register enum values. */
+    DR_REG_STOP_32 = DR_REG_F31,  /**< End of 32-bit register enum values. */
     DR_REG_START_GPR = DR_REG_X0, /**< Start of general register registers. */
     DR_REG_STOP_GPR = DR_REG_X31, /**< End of general register registers. */
     DR_REG_XSP = DR_REG_SP, /**< Platform-independent way to refer to stack pointer. */
@@ -1780,6 +1780,11 @@ typedef enum _dr_opnd_flags_t {
      * SVE predicate constraint
      */
     DR_OPND_IS_PREDICATE_CONSTRAINT = 0x800,
+
+    /**
+     * This is used by RISCV64 for immediates display format.
+     */
+    DR_OPND_IMM_PRINT_DECIMAL = 0x1000,
 } dr_opnd_flags_t;
 
 #ifdef DR_FAST_IR
@@ -2003,6 +2008,18 @@ DR_API
 opnd_t
 opnd_create_immed_int(ptr_int_t i, opnd_size_t data_size);
 
+#ifdef RISCV64
+DR_API
+/**
+ * Returns a signed immediate integer operand with value \p i and size
+ * \p data_size; \p data_size must be a OPSZ_ constant.
+ *
+ * The integer will be formatted as a decimal when disassemble.
+ */
+opnd_t
+opnd_create_immed_int_decimal(ptr_int_t i, opnd_size_t data_size);
+#endif
+
 DR_API
 /**
  * Returns an unsigned immediate integer operand with value \p i and size
@@ -2147,6 +2164,26 @@ opnd_t
 opnd_create_base_disp(reg_id_t base_reg, reg_id_t index_reg, int scale, int disp,
                       opnd_size_t data_size);
 
+#ifdef RISCV64
+DR_API
+/**
+ * Returns a memory reference operand that refers to the address:
+ * - disp(base_reg, index_reg, scale)
+ *
+ * or, in other words,
+ * - base_reg + index_reg*scale + disp
+ *
+ * The operand has data size data_size (must be a OPSZ_ constant).
+ * Both \p base_reg and \p index_reg must be DR_REG_ constants.
+ * \p scale must be either 0, 1, 2, 4, or 8.
+ *
+ * The integer will be formatted as a decimal when disassemble.
+ */
+opnd_t
+opnd_create_base_disp_decimal(reg_id_t base_reg, reg_id_t index_reg, int scale, int disp,
+                              opnd_size_t data_size);
+#endif
+
 DR_API
 /**
  * Returns a memory reference operand that refers to the address:
@@ -2171,7 +2208,8 @@ DR_API
  *    needs to be specified for an absolute address; otherwise, simply
  *    use the desired short registers for base and/or index).
  *
- * (The encoding optimization flags are all false when using opnd_create_base_disp()).
+ * (The encoding optimization flags are all false when using
+ * opnd_create_base_disp()).
  */
 opnd_t
 opnd_create_base_disp_ex(reg_id_t base_reg, reg_id_t index_reg, int scale, int disp,

core/ir/opnd_shared.c

@@ -374,6 +374,16 @@ opnd_create_immed_int(ptr_int_t i, opnd_size_t size)
     return opnd;
 }
 
+#ifdef RISCV64
+opnd_t
+opnd_create_immed_int_decimal(ptr_int_t i, opnd_size_t size)
+{
+    opnd_t opnd = opnd_create_immed_int(i, size);
+    opnd.aux.flags |= DR_OPND_IMM_PRINT_DECIMAL;
+    return opnd;
+}
+#endif
+
 opnd_t
 opnd_create_immed_uint(ptr_uint_t i, opnd_size_t size)
 {
@@ -653,6 +663,17 @@ opnd_create_base_disp(reg_id_t base_reg, reg_id_t index_reg, int scale, int disp
                                         false, false, false);
 }
 
+#ifdef RISCV64
+opnd_t
+opnd_create_base_disp_decimal(reg_id_t base_reg, reg_id_t index_reg, int scale, int disp,
+                              opnd_size_t size)
+{
+    opnd_t opnd = opnd_create_base_disp(base_reg, index_reg, scale, disp, size);
+    opnd.aux.flags |= DR_OPND_IMM_PRINT_DECIMAL;
+    return opnd;
+}
+#endif
+
 static inline void
 opnd_set_disp_helper(opnd_t *opnd, int disp)
 {