Skip to content

Commit

Permalink
Merge pull request #951 from agrevin/if_gen2
Browse files Browse the repository at this point in the history 
Add needed suffixes to accomodate new Py2HWSW syntax
  • Loading branch information
@jjts
jjts committed Sep 20, 2024
2 parents c008c4f + 1d7fecf commit 94ac191
Show file tree
Hide file tree
Showing 67 changed files with 319 additions and 589 deletions.
30 changes: 15 additions & 15 deletions hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ def setup(py_params_dict):
#
attributes_dict["ports"] = [
{
"name": "clk_rst",
"name": "clk_rst_i",
"descr": "Clock and reset",
"signals": [
{"name": "clk", "direction": "input", "width": "1"},
Expand Down Expand Up @@ -85,7 +85,7 @@ def setup(py_params_dict):
],
},
{
"name": "rzqin",
"name": "rzqin_i",
"descr": "",
"signals": [
{"name": "rzqin", "direction": "input", "width": "1"},
Expand Down Expand Up @@ -255,9 +255,9 @@ def setup(py_params_dict):
"AXI_DATA_W": "AXI_DATA_W",
},
"connect": {
"clk_en_rst": "clk_en_rst",
"rs232": "rs232_int",
"axi": "axi",
"clk_en_rst_s": "clk_en_rst",
"rs232_m": "rs232_int",
"axi_m": "axi",
},
"dest_dir": "hardware/common_src",
"iob_soc_params": params,
Expand All @@ -267,7 +267,7 @@ def setup(py_params_dict):
"instance_name": "rst_sync",
"instance_description": "Reset synchronizer",
"connect": {
"clk_rst": "reset_sync_clk_rst",
"clk_rst_s": "reset_sync_clk_rst",
"arst_o": "reset_sync_arst_out",
},
},
Expand All @@ -286,10 +286,10 @@ def setup(py_params_dict):
"AXI_DATA_W": "AXI_DATA_W",
},
"connect": {
"clk_rst": "ddr3_ctr_clk_rst",
"clk_rst_i": "ddr3_ctr_clk_rst",
"general": "ddr3_ctr_general",
"ddr3": "ddr3",
"s0_axi": "axi",
"s0_axi_s": "axi",
},
},
]
Expand All @@ -306,10 +306,10 @@ def setup(py_params_dict):
"AXI_DATA_W": "AXI_DATA_W",
},
"connect": {
"clk": "clk",
"rst": "reset_sync_arst_out",
"s0_axi": "axi",
"m0_axi": "memory_axi",
"clk_i": "clk",
"rst_i": "reset_sync_arst_out",
"s0_axi_s": "axi",
"m0_axi_m": "memory_axi",
},
"num_slaves": 1,
"num_masters": 1,
Expand All @@ -325,9 +325,9 @@ def setup(py_params_dict):
"READ_ON_WRITE": "0",
},
"connect": {
"clk": "clk",
"rst": "reset_sync_arst_out",
"axi": "memory_axi",
"clk_i": "clk",
"rst_i": "reset_sync_arst_out",
"axi_s": "memory_axi",
},
},
]
Expand Down
28 changes: 14 additions & 14 deletions hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@ def setup(py_params_dict):
#
attributes_dict["ports"] = [
{
"name": "clk_rst",
"name": "clk_rst_i",
"descr": "Clock and reset",
"signals": [
{"name": "c0_sys_clk_clk_p", "direction": "input", "width": "1"},
Expand Down Expand Up @@ -274,9 +274,9 @@ def setup(py_params_dict):
"AXI_DATA_W": "AXI_DATA_W",
},
"connect": {
"clk_en_rst": "clk_en_rst",
"rs232": "rs232_int",
"axi": "axi",
"clk_en_rst_s": "clk_en_rst",
"rs232_m": "rs232_int",
"axi_m": "axi",
},
"dest_dir": "hardware/common_src",
"iob_soc_params": params,
Expand All @@ -292,11 +292,11 @@ def setup(py_params_dict):
"AXI_DATA_W": "AXI_DATA_W",
},
"connect": {
"clk_rst_i": "intercon_clk_rst",
"clk_rst_s": "intercon_clk_rst",
"m0_clk_rst": "intercon_m0_clk_rst",
"m0_axi": "memory_axi",
"m0_axi_m": "memory_axi",
"s0_clk_rst": "intercon_s0_clk_rst",
"s0_axi": "axi",
"s0_axi_s": "axi",
},
"num_slaves": 1,
},
Expand All @@ -315,10 +315,10 @@ def setup(py_params_dict):
"AXI_DATA_W": "AXI_DATA_W",
},
"connect": {
"clk_rst": "clk_rst",
"ui_clk_out": "ddr4_ui_clk_out",
"clk_rst_i": "clk_rst_i",
"ui_clk_o": "ddr4_ui_clk_out",
"axi_clk_rst": "ddr4_axi_clk_rst",
"axi": "memory_axi",
"axi_s": "memory_axi",
"ddr4": "ddr4_pins",
},
},
Expand All @@ -335,7 +335,7 @@ def setup(py_params_dict):
"INPUT_PER": 4,
},
"connect": {
"clk_rst_i": "clk_rst",
"clk_rst_i": "clk_rst_i",
"clk_rst_o": "clk_wizard_out",
},
},
Expand All @@ -350,9 +350,9 @@ def setup(py_params_dict):
"READ_ON_WRITE": "1",
},
"connect": {
"clk": "axi_ram_clk",
"rst": "axi_ram_rst",
"axi": "memory_axi",
"clk_i": "axi_ram_clk",
"rst_i": "axi_ram_rst",
"axi_s": "memory_axi",
},
},
]
Expand Down
14 changes: 7 additions & 7 deletions hardware/modules/iob_soc_cache_system/iob_soc_cache_system.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -66,15 +66,15 @@ def setup(py_params_dict):
],
"ports": [
{
"name": "clk_en_rst",
"name": "clk_en_rst_s",
"interface": {
"type": "clk_en_rst",
"subtype": "slave",
},
"descr": "Clock, clock enable and reset",
},
{
"name": "i_bus",
"name": "i_bus_s",
"interface": {
"type": "iob",
"subtype": "slave",
Expand All @@ -85,7 +85,7 @@ def setup(py_params_dict):
"descr": "Instruction bus",
},
{
"name": "d_bus",
"name": "d_bus_s",
"interface": {
"type": "iob",
"subtype": "slave",
Expand All @@ -96,7 +96,7 @@ def setup(py_params_dict):
"descr": "Data bus",
},
{
"name": "axi",
"name": "axi_m",
"interface": {
"type": "axi",
"subtype": "master",
Expand Down Expand Up @@ -154,11 +154,11 @@ def setup(py_params_dict):
"name": "iob_i_d_into_l2_merge",
"instance_name": "iob_i_d_into_l2_merge",
"connect": {
"clk_en_rst": "clk_en_rst",
"reset": "never_reset",
"clk_en_rst_s": "clk_en_rst_s",
"reset_i": "never_reset",
"input_0": "dcache",
"input_1": "icache",
"output": "l2cache",
"output_m": "l2cache",
},
"num_inputs": 2,
"addr_w": MEM_ADDR_W,
Expand Down
34 changes: 17 additions & 17 deletions hardware/modules/iob_soc_sim_wrapper/iob_soc_sim_wrapper.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -45,15 +45,15 @@ def setup(py_params_dict):
#
attributes_dict["ports"] = [
{
"name": "clk_en_rst",
"name": "clk_en_rst_s",
"descr": "Clock, clock enable and reset",
"interface": {
"type": "clk_en_rst",
"subtype": "slave",
},
},
{
"name": "uart",
"name": "uart_s",
"descr": "Testbench uart csrs interface",
"interface": {
"type": "iob",
Expand All @@ -66,7 +66,7 @@ def setup(py_params_dict):
if params["use_ethernet"]:
attributes_dict["ports"] += [
{
"name": "ethernet",
"name": "ethernet_s",
"descr": "Testbench ethernet csrs interface",
"interface": {
"type": "iob",
Expand Down Expand Up @@ -186,9 +186,9 @@ def setup(py_params_dict):
"AXI_DATA_W": "AXI_DATA_W",
},
"connect": {
"clk_en_rst": "clk_en_rst",
"rs232": "rs232",
"axi": "axi",
"clk_en_rst_s": "clk_en_rst_s",
"rs232_m": "rs232",
"axi_m": "axi",
},
"dest_dir": "hardware/common_src",
"iob_soc_params": params,
Expand All @@ -200,9 +200,9 @@ def setup(py_params_dict):
"instance_description": "Testbench uart core",
"csr_if": "iob",
"connect": {
"clk_en_rst": "clk_en_rst",
"cbus": "uart",
"rs232": "rs232_invert",
"clk_en_rst_s": "clk_en_rst_s",
"cbus_s": "uart_s",
"rs232_m": "rs232_invert",
},
},
{
Expand All @@ -216,10 +216,10 @@ def setup(py_params_dict):
"AXI_DATA_W": "AXI_DATA_W",
},
"connect": {
"clk": "clk",
"rst": "rst",
"s0_axi": "axi",
"m0_axi": "memory_axi",
"clk_i": "clk",
"rst_i": "rst",
"s0_axi_s": "axi",
"m0_axi_m": "memory_axi",
},
"num_slaves": 1,
"num_masters": 1,
Expand All @@ -234,9 +234,9 @@ def setup(py_params_dict):
"DATA_WIDTH": "AXI_DATA_W",
},
"connect": {
"clk": "clk",
"rst": "rst",
"axi": "memory_axi",
"clk_i": "clk",
"rst_i": "rst",
"axi_s": "memory_axi",
},
},
]
Expand All @@ -258,7 +258,7 @@ def setup(py_params_dict):
"AXI_DATA_W": "AXI_DATA_W",
},
"connect": {
"clk_en_rst": "clk_en_rst",
"clk_en_rst": "clk_en_rst_s",
"iob": "ethernet",
"axi": "eth_axi",
"mii": "eth_mii_invert",
Expand Down
Loading

0 comments on commit 94ac191

Please sign in to comment.