Fix trap signal of peripherals; Update iob_soc_firmware.S.

README.md

@@ -66,7 +66,7 @@ credential.helper 'cache --timeout=<time_in_seconds>'``
 
 ## Configure your SoC
 
-To configure your system, edit the `iob_soc_setup.py` file, which can be found at the
+To configure your system, edit the `iob_soc.py` file, which can be found at the
 repository root. This file has the system configuration variables;
 hopefully, each variable is explained by a comment.
 
@@ -164,7 +164,7 @@ fi
 
 ## Setup the system
 
-The main configuration for the system is located in the `iob_soc_setup.py` file.
+The main configuration for the system is located in the `iob_soc.py` file.
 
 To set up the system, type:
 
@@ -173,7 +173,7 @@ make setup [<control parameters>]
 ```
 
 `<control parameters>` are system configuration parameters passed in the
-command line, overriding those in the `iob_soc_setup.py` file. Example control
+command line, overriding those in the `iob_soc.py` file. Example control
 parameters are `INIT_MEM=0 USE_EXTMEM=1`. For example,
 
 ```Bash

scripts/iob_soc_create_system.py

@@ -137,8 +137,8 @@ def create_systemv(build_dir, top, peripherals_list, internal_wires=None):
     periphs_wires_str += "    wire cpu_trap_o;\n"
     trap_or_str = "    assign trap_o = cpu_trap_o"
     for peripheral in peripherals_with_trap:
-        periphs_wires_str += f"    wire {peripheral.name}_trap_o;\n"
-        trap_or_str += f"| {peripheral.name}_trap_o"
+        periphs_wires_str += f"    wire {top.upper()}_{peripheral.name}_trap_o;\n"
+        trap_or_str += f"| {top.upper()}_{peripheral.name}_trap_o"
     trap_or_str += ";\n"
 
     # Logic OR of trap signals

software/src/iob_soc_firmware.S

@@ -5,19 +5,20 @@
 .global main
 
 //set stack pointer
+#ifdef USE_EXTMEM //need to set MSB to address external memory
+lui sp, %hi(EXTRA_BASE | 1<<SRAM_ADDR_W)
+addi sp, sp, %lo(EXTRA_BASE | 1<<SRAM_ADDR_W)
+#else
 lui sp, %hi(1<<SRAM_ADDR_W)
 addi sp, sp, %lo(1<<SRAM_ADDR_W)
+#endif
 
 //call main
 jal ra, main
 
 //reboot to run bootloader
 li s5, 3 //cpu_rst_req=1, boot=1
-#ifdef USE_EXTMEM //need to set MSB to address internal mem and boot controller
-li s6, EXTRA_BASE | BOOTCTR_BASE
-#else
 li s6, BOOTCTR_BASE
-#endif
 sw s5, 0(s6)
 
 ebreak