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[general] added cke_i to iob_soc #592

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AndreMerendeira
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Comment on lines +97 to +98
.clk(clk_i),
.rst(arst_i),
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@arturum1 arturum1 Aug 25, 2023

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These lines are used to generate the interconnect instance in every wrapper that needs one.
Therefore, the signals generated must have a common name to all wrappers.

Currently, the iob_soc_sim_wrapper.v and the iob_soc_fpga_wrapper.v of the CYCLONEV are the only wrappers that use this interconnect, and they contain the common wires named clk and rst.
They do NOT contain the arst_i signal, therefore trying to generate an interconnect with this signal will give an error (that is why those checks are failing).

I suggest keeping the common clk and rst signals.

Suggested change
.clk(clk_i),
.rst(arst_i),
.clk(clk),
.rst(rst),

Another solution would be to make sure the clk_i and arst_i signals exist in the wrappers.

@jjts
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jjts commented Aug 26, 2023 via email

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jjts commented Aug 26, 2023

Checks fail , can't merge

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jjts commented Sep 20, 2023

the author has no time to fix this - closing

@jjts jjts closed this Sep 20, 2023
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3 participants