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[general] added cke_i to iob_soc #592

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[general] added cke_i to iob_soc #592

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[general] added cke_i to iob_soc
AndreMerendeira Aug 25, 2023
f6efbed
Merge branch 'python-setup' of github.com:AndreMerendeira/iob-soc int…
AndreMerendeira Aug 25, 2023
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1 change: 1 addition & 0 deletions hardware/fpga/quartus/CYCLONEV-GT-DK/iob_soc_fpga_wrapper.v
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Original file line number Diff line number Diff line change
Expand Up @@ -124,6 +124,7 @@ module iob_soc_fpga_wrapper (
//`endif
`include "iob_soc_pportmaps.vs"
.clk_i (clk),
.cke_i (1'b1),
.arst_i(rst),
.trap_o(trap)
);
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1 change: 1 addition & 0 deletions hardware/fpga/vivado/AES-KU040-DB-G/iob_soc_fpga_wrapper.v
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Expand Up @@ -120,6 +120,7 @@ module iob_soc_fpga_wrapper (
//`endif
`include "iob_soc_pportmaps.vs"
.clk_i (clk),
.cke_i (1'b1),
.arst_i(rst),
.trap_o(trap)
);
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1 change: 1 addition & 0 deletions hardware/fpga/vivado/BASYS3/iob_soc_fpga_wrapper.v
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Expand Up @@ -36,6 +36,7 @@ module iob_soc_fpga_wrapper (
//
iob_soc iob_soc (
.clk_i (clk),
.cke_i (1'b1),
.arst_i (sys_rst),
.trap_o (trap),
//UART
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1 change: 1 addition & 0 deletions hardware/simulation/src/iob_soc_sim_wrapper.v
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Expand Up @@ -63,6 +63,7 @@ module iob_soc_sim_wrapper (
) iob_soc0 (
`include "iob_soc_pportmaps.vs"
.clk_i (clk),
.cke_i (1'b1),
.arst_i(rst),
.trap_o(trap_o)
);
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3 changes: 0 additions & 3 deletions hardware/src/iob_soc.v
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Expand Up @@ -26,9 +26,6 @@ module iob_soc #(
wire boot;
wire cpu_reset;

wire cke_i;
assign cke_i = 1'b1;

//
// CPU
//
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6 changes: 6 additions & 0 deletions iob_soc.py
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Expand Up @@ -318,6 +318,12 @@ def _setup_ios(cls):
"n_bits": "1",
"descr": "System clock input",
},
{
"name": "cke_i",
"type": "I",
"n_bits": "1",
"descr": "System clock enable",
},
{
"name": "arst_i",
"type": "I",
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4 changes: 2 additions & 2 deletions scripts/iob_soc_create_wrapper_files.py
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Expand Up @@ -94,8 +94,8 @@ def create_interconnect_instance(out_dir, name, num_extmem_connections):
.S_COUNT ({num_extmem_connections}),
.M_COUNT (1)
) system_axi_interconnect (
.clk(clk),
.rst(rst),
.clk(clk_i),
.rst(arst_i),
Comment on lines +97 to +98
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@arturum1 arturum1 Aug 25, 2023 •
edited
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These lines are used to generate the interconnect instance in every wrapper that needs one.
Therefore, the signals generated must have a common name to all wrappers.

Currently, the iob_soc_sim_wrapper.v and the iob_soc_fpga_wrapper.v of the CYCLONEV are the only wrappers that use this interconnect, and they contain the common wires named clk and rst.
They do NOT contain the arst_i signal, therefore trying to generate an interconnect with this signal will give an error (that is why those checks are failing).

I suggest keeping the common clk and rst signals.

Suggested change
.clk(clk_i),
.rst(arst_i),
.clk(clk),
.rst(rst),

Another solution would be to make sure the clk_i and arst_i signals exist in the wrappers.


// Need to use manually defined connections because awlock and arlock of interconnect is only on bit for each slave
.s_axi_awid (axi_awid), //Address write channel ID.
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