merge(main); Merge main into if_gen #623
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update(LIB, UART, CACHE): submodules
This reverts commit 0cd8674. The `axi_m_port` interface of iob-soc is a bus with multiple `axi_m` interfaces. Therefore, we should specify that the `ext_mem` component of iob-soc only uses the first interface of that bus. Without the bit select (even for 1 bit signals), the Verilog will assign the entire bus to the `ext_mem` component.
- Dynamically remove `[0+:1]` part select in AXI connections of ext_mem0 in iob_soc.v template if the bus size is 1 (because we can't use part select in scalar values).
- fpga-test checks for "Test passed" after regular fpga-run
feat(fpga): add fpga test target, update CI to run `fpga-test`
Allow override of `N_SLAVES` macro by subclasses; Update `axi_m_port` part select script.
[LIB] fixed spyglass and alint tcl
- update CI to run individual fpga tests - `fpga-test` target always runs 4 predefined fpga-tests
fix(CI): run individual fpga tests
- update software macro addresses for software accessible registers to have `_ADDR` sufix
- remove unused SWREG_rvalid_rd signal. Now swreg module generates rvalid signal for all software accessible registers
fix(SWREG): <SWREG>_ADDR as macro address; remove unused <SWREG>_rvalikd_rd signal
[mkregs] removed unused pc
- update AXI submodule to have iob_module structure for axi_ram and
axi_interconnect modules
- passes LIB modules simulation tests
- remove redundant interface names
- update interface generation to copy files from setup dir to build
dir
- passes UART core simulation tests
- update CACHE submodule
- working SOC tests
- LIB fixes:
- remove duplicated iob_tasks
- working LIB and UART tests NOTE: still need to merge CACHE with latest main branch
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Note: probably @arturum1 should review this PR