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Move iob_soc to lib and rename it to iob_system; Replace axil peripheral cbus by iob interface. #953

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merged 13 commits into from
Oct 2, 2024

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@arturum1 arturum1 commented Sep 30, 2024

  • Move iob_soc module to lib and rename it to iob_system.
    New iob_system can be used as a tool to create SoCs.
    Added new template iob_soc.py, that uses py2hwsw parent attribute to create a SoC based on iob_system.
  • Create bus_width_converter lib module to connect two py2 buses with different widths without verilog warnings.
  • Add support for is_peripheral attribute in iob_system blocks.
  • Replace axil interfaces of peripherals cbus by iob interfaces.

- This module will be used to connect two buses with different widths with
py2. Otherwise we would need to connect those buses signals individually
using snippets (to trim their width).
- Fix axil2iob interface widths.
- Format verilog code of iob_fifo_sync.v
New 'is_peripheral' block attribute in iob_soc blocks list is used to
identify peripheral blocks.
These blocks will have their cbus connection added automatically to the
system's pbus_split.
Other ports should be connected manually.
The 'iob_soc' core is now named 'iob_system' and was moved to lib.
The future 'iob_soc' core will be an extension to the current 'iob_system'.
Setup of iob_soc with iob_system as parent is working.
Fix some verilog warnings with bit slicing.
Fix lib modules.
@arturum1 arturum1 changed the title Move iob_soc to lib and rename it to iob_system; Add bus_width_converter; Move iob_soc to lib and rename it to iob_system; Replace axil peripheral cbus by iob interface. Oct 1, 2024
Add iob_soc_firmware.c as an example custom firmware to override default
one from iob_system.

This custom firmware prints "Hello world from IOb-SoC!"
…b_system.

TODO: Find a way of automating cbus connections of child module (iob-soc).
These connections are normally automated by iob-system utils, but those
scripts don't have access to the child module attributes.
Increase timeout to allow iob_system module test to run.

Update py2hwsw.
Pass ADDR_W to peripherals matching output of pbus split.
This fixes cbus verilog warnings.

Also update peripherals to support ADDR_W and ignore unused bits.
This allows lib ghactions test to run faster.
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