Add parent attribute; Add bit slicing and concatenations in port connections; Add regfile in CSRs and asym FIFOs.
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No longer use python parameters for auto-csrs.
Now the user provides a CSR with the correct "type" ("INTERRUPT",
"FIFO_R", "AFIFO_W", ...), and the scripts will replace this one by the
complete CSRs for the given type.
If user sets a write register with 'log2n_items' > 0, then csrs.py will generate the regfile inside the csrs module. All registers from regfile can be read in parallel. A port signal is created for each register in the regfile. Example, if we create a CSR, named 'reg', with 'log2n_items' = 2, then the following port signals will be available in the csrs module: reg_0_wr reg_1_wr reg_2_wr reg_3_wr If the user creates a CSR with `autoreg = False`, then the regfile is not generated. The csrs module continues to generate a single port for this regfile, since the signals come from the CPU, and the CPU can only address one register at a time. If the user creates a CSR of type "R" (read register), then the regfile is not generated. This is because read registers should always be implemented by user logic. The csrs module only generates wires to read from the user logic's regfile. Note 1: If we have `autoreg = True`, and type "RW", then the csrs module will generate the regfile for the write part, but will continue to have normal wires for the read part. Note 2: The user logic can find out which register from the regfile is being addressed by using the `iob` output port of the csrs module. (The `iob` output port is always available to user logic, even if csr_if is set to another interface). Related to issues: #33 IObundle/iob-soc#719
New FIFOs are created by specifying a single CSR of one of the following types: - FIFO_R - FIFO_W - AFIFO_R - AFIFO_W The csrs module will replace this CSR by the corresponding FIFO CSRs, and will instantiante the FIFO inside the verilog module. TODO: AFIFOs not working yet; FIFO size not adjustable yet.
…ctions.
Using an optional tuple in the port connection, we can specify the bit
slice for each singal.
Example of modifying bit slice for signals `axi_arlock` and `axi_awlock`
of wire `axi_m`:
"mem_axi_m": ("axi_m", "axi_arlock[0]", "axi_awlock[0]")
Removed auto-bit slicing previously implemented in py2hwsw (was only
used to auto-trim most significant bits).
New bit slice specification in port connections in generic. Now, it also supports bit concatenations. Fix verilog warnings in axi2iob generated by csrs.
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Used in PR IObundle/iob-soc#953