NanoMips: OR combine optimization

llvm/lib/Target/Mips/MipsISelLowering.cpp

@@ -1046,8 +1046,26 @@ static SDValue attemptOrToIns(SDValue &And, SDValue &Right, SDNode *N,
   if (!(CN = dyn_cast<ConstantSDNode>(And.getOperand(1))))
     return SDValue();
   unsigned Mask0 = ~CN->getZExtValue();
-  if (!isShiftedMask(Mask0, SMPos0, SMSize0))
-    return SDValue();
+
+  KnownBits KnownMaskBits = DAG.computeKnownBits(SDValue(CN, 0));
+  APInt maxValue = KnownMaskBits.getMaxValue();
+  unsigned int MaxNumOfActiveBitsInMask = maxValue.getActiveBits();
+
+  // If the mask value fits into 16 bits, trim the leading ones.
+  // Leading ones were made after negating zero expanded 16 bit value.
+  // This enables the function isShiftedMask() to recognize 16 bit masks as
+  // valid.
+  // TODO: Support the case when there are two two consecutive OR instructions
+  // and two masks whose value fits in 16 bits.
+  if (MaxNumOfActiveBitsInMask <= 16) {
+    uint16_t Mask0_16 = Mask0;
+    if (!isShiftedMask(Mask0_16, SMPos0, SMSize0))
+      return SDValue();
+  } else if (MaxNumOfActiveBitsInMask <= 32) {
+    uint32_t Mask0_32 = Mask0;
+    if (!isShiftedMask(Mask0_32, SMPos0, SMSize0))
+      return SDValue();
+  }
 
   SDLoc DL(N);
   EVT ValTy = N->getValueType(0);
@@ -1129,9 +1147,20 @@ static SDValue attemptOrToIns(SDValue &And, SDValue &Right, SDNode *N,
     if (!(CN = dyn_cast<ConstantSDNode>(Right.getOperand(1))))
       return SDValue();
     unsigned ShiftAmount = CN->getZExtValue();
-    // Second check makes sure that all upper bits are picked up.
-    if ((ShiftAmount != SMPos0) || (SMPos0 + SMSize0 != TSize))
+
+    if ((ShiftAmount != SMPos0))
       return SDValue();
+
+    if ((SMPos0 + SMSize0 != TSize)) {
+      // If a register holds a value that is zero extended
+      // and if the actual size of that value can fit in SMSize0
+      // then we will allow replacement with the INS instruction
+      // because we are sure that we have only leading zeros
+      KnownBits Known = DAG.computeKnownBits(Right.getOperand(0));
+      if (Known.getMaxValue().getActiveBits() > SMSize0)
+        return SDValue();
+    }
+
     return DAG.getNode(MipsISD::Ins, DL, ValTy, Right.getOperand(0),
                        DAG.getConstant(SMPos0, DL, MVT::i32),
                        DAG.getConstant(SMSize0, DL, MVT::i32),

llvm/test/CodeGen/Mips/nanomips/ins.ll

@@ -60,3 +60,43 @@ define i32 @ins6(i32 %a, i32 %b) {
   %or = or i32 %and1, %shift
   ret i32 %or
 }
+
+define i32 @ins7(i32 %a, i8 %b) {
+  ; CHECK: ins $a0, $a1, 16, 8
+  %and1 = and i32 %a, 4278255615 ; 0xff00ffff
+  %conv = zext i8 %b to i32
+  %shift = shl i32 %conv, 16
+  %or = or i32 %and1, %shift
+  ret i32 %or
+}
+
+define i32 @ins8(i32 %a, i16 %b) {
+  ; CHECK: ins $a0, $a1, 8, 16
+  %and1 = and i32 %a, 4278190335 ; 0xff0000ff
+  %conv = zext i16 %b to i32
+  %shift = shl i32 %conv, 8
+  %or = or i32 %and1, %shift
+  ret i32 %or
+}
+
+define i32 @ins9(i32 %a, i8* %b) {
+  ; CHECK: ins $a0, $a1, 16, 8
+  %val = load i8, i8* %b
+  %and1 = and i32 %a, 4278255615 ; 0xff00ffff
+  %conv = zext i8 %val to i32
+  %shift = shl i32 %conv, 16
+  %or = or i32 %and1, %shift
+  ret i32 %or
+}
+
+define i32 @ins10(i32 %a, i16* %b) {
+  ; CHECK: ins $a0, $a1, 8, 16
+  %val = load i16, i16* %b
+  %and1 = and i32 %a, 4278190335 ; 0xff0000ff
+  %conv = zext i16 %val to i32
+  %shift = shl i32 %conv, 8
+  %or = or i32 %and1, %shift
+  ret i32 %or
+}
+
+